3 ms·
Well of course SIMD performance is part of the "hard part", because it implies things like very wide cache access, including perhaps unaligned access, high band
by BeeOnRope 8y ago
Well of course SIMD performance is part of the "hard part", because it implies things like very wide cache access, including perhaps unaligned access, high bandwidth between cache levels, wide register files, etc.
Plus a sane ISA extension strategy that actually gets people to use your SIMD instructions helps a lot (Intel hasn't done well here, but so far neither has ARM e.g., with almost non-existent support for SVE).
SIMD performance is one place that Intel is still fairly far ahead of both AMD and the ARM competition (with Apple far out ahead in that group).
- BubRoss 8y agoI'm not sure what a sane ISA has to do here, the parent was comparing a SIMD accelerated program to a non-SIMD program and using that to compare two CPU architectures. Does that seem right to you?
- BeeOnRope 8y agoPerhaps not, but I was referring only to the assertion that wide SIMD is not in the "hard part" of designing a CPU. I happen to agree with the GP that comparing SIMD accelerated to not can give a misleading picture, and so deserves to be noted - especially when one party has relevant SIMD instructions but they weren't used for some reason.