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The datasheet says it features a "Cortex M4 with 16 KB of instruction cache and 16 KB of data cache". As far as I know, M4 don't have L1 cache. Maybe they're us
by Ecco 8y ago
The datasheet says it features a "Cortex M4 with 16 KB of instruction cache and 16 KB of data cache". As far as I know, M4 don't have L1 cache. Maybe they're using an M7? Or there's just simply no cache?
https://coral.withgoogle.com/tutorials/devboard-datasheet/ https://coral.withgoogle.com/tutorials/devboard-datasheet/
- JosephRedfern 8y agoI don't think the M4 is a typo. Apparently it's based on the NXP i.MX 8M, who's block diagram definitley states Cortex-M4 w/ 16K L1 Cache: https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/i.mx-applications-processors/i.mx-8-processors/i.mx-8m-family-armcortex-a53-cortex-m4-audio-voice-video:i.MX8M https://www.nxp.com/products/processors-and-microcontrollers.... M4 application notes (http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dai0321a/BIHEADII.html http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc....) says the M{-0..4} doesn't have any internal cache, but that it can be provided by the SoC. Presumably that's what's happening here -- although it seems weird that this can be called an L1 Cache (although I'm by no means an expert on this so can't really comment!).
- emcq 8y agoThe NXP i.MX 8M SOC has a Cortex-a53 and M4F.
- makapuf 8y agoMaybe they're not talking about ram but Flash I/D cache. By example Stm32f4 come with flash cache (they call it ART accelerator) to prefetch instructions from flash to enable "zero" wait states.