4 ms·

> You can process four independent instructions per cycle in parallel is this down to pipelining, or is that separate?

gpderetta 8y ago
Actual redundant hardware. There are multiple ALUs for example (although not all equal), multiple load/store units. But the bottleneck that prevents of going wider than 4 is often the rename up to 4 registers per clock.
jcranmer 8y ago
Modern processors are superscalar. What this means is that you have multiple independent execution units that can be scheduled each cycle. On Skylake, for instance, the execution units are: Port 0: int ALU, FP ALU, vector ALU, integer multiply/divide, branch Port 1: int ALU, FP ALU, vector ALU Port 2: Load unit Port 3: Load unit Port 4: Store unit Port 5: integer ALU, vector ALU Port 6: integer ALU, branch Port 7: Store unit [address component] Every instruction (or, more accurately, every micro-op; instructions don't exist at this point) can get scheduled onto one of these ports if that port has the capability to process it. Of course, there's also a limitation on the abilities of the instruction decode unit on how many instructions it can decode and convert into micro-ops each cycle.
brucedawson 8y ago
Pipelining is necessary is well, but super-scalar is the key ingredient here - parallelism. Pipelining means that instruction fetch, decode, execution, and retirement are done in separate stages, each one taking at least one cycle. Super-scalar/parallelism means that there are multiple units for all of these stages so the CPU can fetch many instructions in parallel, decode many instructions in parallel, etc. The cool/critical thing here is that many Intel CPUs can execute three XOR instructions in parallel but can retire four. Because the CPU recognizes XOR of an instruction with itself as a special case it skips the execution stage and can then process four per cycle. Or, more likely in real code, the execution units are available for other instructions to use.
- a1369209993 8y ago
  Strictly speaking pipelining isn't actually necessary, it's just hard to imagine why you'd bother with superscalar execution without first exhausting the relatively-lower-hanging-fruit of pipelining.

Actual redundant hardware. There are multiple ALUs for example (although not all equal), multiple load/store units. But the bottleneck that prevents of going wider than 4 is often the rename up to 4 registers per clock.

jcranmer 8y ago

Modern processors are superscalar. What this means is that you have multiple independent execution units that can be scheduled each cycle. On Skylake, for instance, the execution units are: Port 0: int ALU, FP ALU, vector ALU, integer multiply/divide, branch Port 1: int ALU, FP ALU, vector ALU Port 2: Load unit Port 3: Load unit Port 4: Store unit Port 5: integer ALU, vector ALU Port 6: integer ALU, branch Port 7: Store unit [address component] Every instruction (or, more accurately, every micro-op; instructions don't exist at this point) can get scheduled onto one of these ports if that port has the capability to process it. Of course, there's also a limitation on the abilities of the instruction decode unit on how many instructions it can decode and convert into micro-ops each cycle.

brucedawson 8y ago

Pipelining is necessary is well, but super-scalar is the key ingredient here - parallelism. Pipelining means that instruction fetch, decode, execution, and retirement are done in separate stages, each one taking at least one cycle. Super-scalar/parallelism means that there are multiple units for all of these stages so the CPU can fetch many instructions in parallel, decode many instructions in parallel, etc. The cool/critical thing here is that many Intel CPUs can execute three XOR instructions in parallel but can retire four. Because the CPU recognizes XOR of an instruction with itself as a special case it skips the execution stage and can then process four per cycle. Or, more likely in real code, the execution units are available for other instructions to use.

a1369209993 8y ago
Strictly speaking pipelining isn't actually necessary, it's just hard to imagine why you'd bother with superscalar execution without first exhausting the relatively-lower-hanging-fruit of pipelining.