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Here are 3 errata I picked from the Xeon E5 series [0]: > REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page Boundaries with Inconsistent Memo
by tlb 8y ago
Here are 3 errata I picked from the Xeon E5 series [0]:
> REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page Boundaries with Inconsistent Memory Types may use an Incorrect Data Size or Lead to Memory-Ordering Violations
> Changing the Memory Type for an In-Use Page Translation May Lead to Memory-Ordering Violations
> When a Link is Degraded on a Port due to PCIe* Signaling Issues, Correctable Receiver Errors May be Reported on The Neighboring Port
The 1st is related to ISA complexity, the 2nd and 3rd aren't.
Based on a quick scan, I think 24 of the first 100 errata are ISA-complexity related. So "meaningfully easier" might be justified, but many problems come from peripherals or the MMU rather than the instruction decoder.
[0] https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/xeon-e5-family-spec-update.pdf https://www.intel.com/content/dam/www/public/us/en/documents...
- bem94 8y agox86 is undoubtedly a very complex beast, so ARM/MIPS are fairer comparisons. Never mind the fact that a Xeon CPU is boggling complex on top of that. I think you are right about how problems are more likely to come from interractions with peripherals, especially the MMU. Most of these things are not architecturally specified, so it's an orthogonal problem to ISA complexity. Bugs in instruction decoders are something of a false flag in my opinion. They are no less important than other bugs, but they are much easier to find as well, because the problem space is more manageable. A little more complexity in an instruction decoder is not, in my opinion, enough justification to exclude otherwise useful instructions or functionality.