> I'd expect compression to be too expensive, transistor wise, for many roles where you'd use an ARM Cortex M2 or such... Decoding the "compressed" instruction

> I'd expect compression to be too expensive, transistor wise, for many roles where you'd use an ARM Cortex M2 or such... Decoding the "compressed" instructions is actually pretty straightforward, it doesn't add much complexity to a design. ARM Cortex M0+/M3/M4 implements a similar (but more complex) "compressed" instruction set called Thumb, and comparable RISC-V cores available from SiFive are smaller, faster, and more efficient. In a very small RISC-V core by the venerable Clifford Wolf called PicoRV32 [0], you can look at the complexity introduced by configuring it with the COMPRESSED_ISA option. > ...and program memory is at a premium in those places. Program memory is one thing, but on processors of all sizes, code size has a big impact on performance in common types of program. [0]: https://github.com/cliffordwolf/picorv32 https://github.com/cliffordwolf/picorv32