3 ms·
It's not just 9/8 more RAM, but 9/8 more memory bandwidth on the bus. So, yes, a pretty nasty performance hog for typical use.
by zozbot123 8y ago
It's not just 9/8 more RAM, but 9/8 more memory bandwidth on the bus. So, yes, a pretty nasty performance hog for typical use.
- p1necone 8y agoI wonder how feasible it would be to build ECC ram where you could toggle the ECC part and just use the extra capacity if you so wished.
- WrtCdEvrydy 8y agoECC is a hardware level implementation usually.
- shawnz 8y agoBut why does it have to be implemented in the DIMMs? Why not in the memory controller, such that any RAM could be used with or without parity?
- WrtCdEvrydy 8y agoIf you do that, you're moving the cost on to the motherboards and increasing the cost for something most consumers won't get any advantage out of.
- agapon 8y agoECC logic is implemented in the memory controller (in the CPU these days). The ECC DIMM just provides extra chips to store ECC bits. And the motherboard, if it supports ECC, provides just extra data lanes that connect the extra DIMM chips to the appropriate pins on the CPU.
- vbezhenar 8y agoIs your typical performance limited by memory bandwidth? Or rather by latency?
- kop316 8y agoOnce again...that's use case. But ECC will affect both. You have 9/8 more bits you have to get from RAM, then you have to doo the ECC calculation for each byte
- Unklejoe 8y agoThe bus is also 8 bits wider, so it’s a wash.