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So my guess is that Chisel is one of the many responses to the two horrors that are VHDL and Verliog. Unfortunately, Chisel is built on Scala, and I have no in

So my guess is that Chisel is one of the many responses to the two horrors that are VHDL and Verliog. Unfortunately, Chisel is built on Scala, and I have no interest in learning Scala. Though I'm intrigued by the claim of using generators and not instances, and would be interested in a white paper that explains it in PL-agnostic terms (PL: programming language). Also have on my to-do list MyHDL [1], a Python solution to the same problem. (has anyone tried it and found to be better than VHDL/Verilog?) [1] http://www.myhdl.org/ http://www.myhdl.org/

Cyph0n 8y ago
> Unfortunately, Chisel is built on Scala, and I have no interest in learning Scala. That's a strange reason for not wanting to reap the benefits of Chisel. Care to explain your rationale? There is another compile-to-HDL "language" called SpinalHDL[1], so I would actually argue that Scala's metaprogramming features seem to be a good fit for this usecase. [1] https://github.com/SpinalHDL/SpinalHDL https://github.com/SpinalHDL/SpinalHDL
- zozbot123 8y ago
  Rust has extensive metaprogramming features as well, so hopefully we'll be able to build a comparable framework starting from that.
  - Cyph0n 8y ago
    I love Rust just as much as the next guy, but not everything needs to be rewritten in Rust...
deleted 8y ago
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zavi 8y ago
> ...and I have no interest in learning... Single biggest red flag when hiring engineers.
- ralusek 8y ago
  Good thing they're not asking for a job.
pedroaraujo 8y ago
I get the impression that people who talk about the "horrors" that are VHDL and Verilog for hardware design are software developers who have little to no knowledge about hardware design processes. There are reasons why VHDL/Verilog are still in use in the industry and why high-level synthesis hasn't taken off. VHDL/Verilog for hardware design is not broken. I won't claim that there isn't space for improvement (because there is) but there isn't anything fundamentally broken in them. They are fit for the purpose and they fulfill all of the needs we have. What could be massively improved is actually the functional verification languages we use, SystemVerilog for verification is in serious need of an overhaul.
- dnautics 8y ago
  OK. I'll bite. I only have experience with verilog, but it's basically uncomfortable to work with in the sense that there are absolutely no developer ergonomics. We're well into the 21st century and you'd think that our HDLs would learn from everything that the software world has learned. 1) the syntax is very finicky (slighttly more so than C, I'd say). Most software languages (thanks to more experience with parsers and compilers) have moved on from things like requiring semicolons, verilog has not. 2) writing tests is awful. Testbenches are crazy confusing. Much better would be some sort of unit testing system that does a better job of segregating of what constitutes "testing code" versus the "language of the gates". You would have a hard time doing something like, say, property testing using verilog. 3) there isn't a consistent build/import story with verilog. Once worked with an engineer that literally used perl as a verilog metaprogramming language. His codebase had a hard-to-find perl frankenbug which sometimes inserted about 10k lines of nonsense (which somehow still assembled a correct netlist!) but caused gate timings to severely miss and the footprint to be bloated. It took the other hardware developers one week to track down the error. None of these things have anything to do with the fundamental difference between software and hardware development. For chisel: at least to some degree, you can get some developer ergonomics from the Scala ecosystem, and do most of your unit, functional, in integration testing outside of verilog, in chisel, and last-minute autogenerate verilog and do a second round of testing to make sure chisel did everything right. It's the same reason why people do things like "use elm to develop frontend, compiling down to javascript" and it's a perfectly valid strategy.
dnautics 8y ago
if you'd like something on a to-do, I built this once, but it was a long time ago, julia has gotten a lot better, and it only does combinatorial logic (not sequential logic). I had an idea of how to do sequential logic using lambda closures in julia, but I never got around to it. https://github.com/interplanetary-robot/Verilog.jl https://github.com/interplanetary-robot/Verilog.jl
pjmlp 8y ago
VHDL is quite nice as Ada influenced language, not sure what is horror about it.
xvilka 8y ago
This is why the suggestion to create language/tooling neutral intermediate representation, based on FIRRTL[1]. [1] https://github.com/SymbiFlow/ideas/issues/19 https://github.com/SymbiFlow/ideas/issues/19

Cyph0n 8y ago

> Unfortunately, Chisel is built on Scala, and I have no interest in learning Scala. That's a strange reason for not wanting to reap the benefits of Chisel. Care to explain your rationale? There is another compile-to-HDL "language" called SpinalHDL[1], so I would actually argue that Scala's metaprogramming features seem to be a good fit for this usecase. [1] https://github.com/SpinalHDL/SpinalHDL https://github.com/SpinalHDL/SpinalHDL

zozbot123 8y ago
Rust has extensive metaprogramming features as well, so hopefully we'll be able to build a comparable framework starting from that.
- Cyph0n 8y ago
  I love Rust just as much as the next guy, but not everything needs to be rewritten in Rust...

deleted 8y ago

[deleted]

zavi 8y ago

> ...and I have no interest in learning... Single biggest red flag when hiring engineers.

ralusek 8y ago
Good thing they're not asking for a job.

pedroaraujo 8y ago

I get the impression that people who talk about the "horrors" that are VHDL and Verilog for hardware design are software developers who have little to no knowledge about hardware design processes. There are reasons why VHDL/Verilog are still in use in the industry and why high-level synthesis hasn't taken off. VHDL/Verilog for hardware design is not broken. I won't claim that there isn't space for improvement (because there is) but there isn't anything fundamentally broken in them. They are fit for the purpose and they fulfill all of the needs we have. What could be massively improved is actually the functional verification languages we use, SystemVerilog for verification is in serious need of an overhaul.

dnautics 8y ago
OK. I'll bite. I only have experience with verilog, but it's basically uncomfortable to work with in the sense that there are absolutely no developer ergonomics. We're well into the 21st century and you'd think that our HDLs would learn from everything that the software world has learned. 1) the syntax is very finicky (slighttly more so than C, I'd say). Most software languages (thanks to more experience with parsers and compilers) have moved on from things like requiring semicolons, verilog has not. 2) writing tests is awful. Testbenches are crazy confusing. Much better would be some sort of unit testing system that does a better job of segregating of what constitutes "testing code" versus the "language of the gates". You would have a hard time doing something like, say, property testing using verilog. 3) there isn't a consistent build/import story with verilog. Once worked with an engineer that literally used perl as a verilog metaprogramming language. His codebase had a hard-to-find perl frankenbug which sometimes inserted about 10k lines of nonsense (which somehow still assembled a correct netlist!) but caused gate timings to severely miss and the footprint to be bloated. It took the other hardware developers one week to track down the error. None of these things have anything to do with the fundamental difference between software and hardware development. For chisel: at least to some degree, you can get some developer ergonomics from the Scala ecosystem, and do most of your unit, functional, in integration testing outside of verilog, in chisel, and last-minute autogenerate verilog and do a second round of testing to make sure chisel did everything right. It's the same reason why people do things like "use elm to develop frontend, compiling down to javascript" and it's a perfectly valid strategy.

dnautics 8y ago

if you'd like something on a to-do, I built this once, but it was a long time ago, julia has gotten a lot better, and it only does combinatorial logic (not sequential logic). I had an idea of how to do sequential logic using lambda closures in julia, but I never got around to it. https://github.com/interplanetary-robot/Verilog.jl https://github.com/interplanetary-robot/Verilog.jl

pjmlp 8y ago

VHDL is quite nice as Ada influenced language, not sure what is horror about it.

xvilka 8y ago

This is why the suggestion to create language/tooling neutral intermediate representation, based on FIRRTL[1]. [1] https://github.com/SymbiFlow/ideas/issues/19 https://github.com/SymbiFlow/ideas/issues/19