> because when AMD tries the second time around [0] to do a pin-compatible RISC (maybe this time it's one of the Zen 4 platforms or whatever), [...] > [0]: htt

> because when AMD tries the second time around [0] to do a pin-compatible RISC (maybe this time it's one of the Zen 4 platforms or whatever), [...] > [0]: https://www.extremetech.com/computing/181867-amds-project-skybridge-new-arm-and-x86-chips-that-are-pin-compatible https://www.extremetech.com/computing/181867-amds-project-sk... The mentioned Project Skybridge is dead: https://wccftech.com/amd-cancelled-skybridge-glofo-terminated-20nm/ https://wccftech.com/amd-cancelled-skybridge-glofo-terminate...