3 ms·

Oh, wow. Out of order instruction processing makes sense now, assuming that helps compensate for lightspeed latency.

• scott_s 16y ago
  Actually, out-of-order instruction pipelines are limited by this problem because the more instructions you allow in-flight, the more stages in the pipeline. The more stages in the pipeline, the more physical distance information much travel on the chip. So lengthening the instruction pipeline runs into fundamental problems. Hence the move to multicore.
  • goalieca 16y ago
    Also, the number of transistors in the path to switching the right bits from memory (even cache) is also getting comparable to the length of pipeline sections.
  • Nessuss 16y ago
    And now we have power problems, so you can't have everything on at once. Such is life.