3 ms·
Modern x86 is not RISC under the covers. There’re instructions combining a dozen of math operations and also RAM loads, that on modern CPUs decode into just a
by Const-me 8y ago
Modern x86 is not RISC under the covers.
There’re instructions combining a dozen of math operations and also RAM loads, that on modern CPUs decode into just a single micro-op.
Example: https://www.felixcloutier.com/x86/vfmadd132ps:vfmadd213ps:vfmadd231ps https://www.felixcloutier.com/x86/vfmadd132ps:vfmadd213ps:vf... The AVX version computes x=a*b+pointer[i], for 8 independent SIMD lanes.
If you call that amount of stuff in a single micro-op “reduced instruction set” I wonder what exactly is the meaningful definition that you referred to?