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https://github.com/westerndigitalcorporation/swerv-ISS https://github.com/westerndigitalcorporation/swerv-ISS

• KSteffensen 8y ago
  From a quick look this is a reference model, not a testbench. There is a lot of work needed, writing testbench environment, test cases, analyzing and writing coverage models etc. before the Verilog code can be considered verified and ready for ASIC tape-out. From my experience writing the design RTL code is at most 25% of the man hours. The rest is verification and some synthesis backend work.