3 ms·
> Since RISC-V uses Chisel instead of Verilog What do you mean? The core here is entirely Verilog/SystemVerilog
by dooglius 8y ago
> Since RISC-V uses Chisel instead of Verilog
What do you mean? The core here is entirely Verilog/SystemVerilog
- mepian 8y agoI presume the parent generalized their experience with the BOOM and Rocket implementations of RISC-V, which do use Chisel, to the entire architecture.
- eBombzor 8y agoSorry I am an idiot how do I edit/delete my comment so I can erase this misinformation?
- yjftsjthsd-h 8y agoUnfortunately, if you don't see an edit button on the comment then you can't edit it anymore. But props for admitting you're wrong and trying to correct it :-)