4 ms·
Agreed. Dataflow is hard to program. A classic Verilog example: always @(posedge clk) begin b <= a; a <= b; end You know how SW developers like th
by alain94040 16y ago
Agreed. Dataflow is hard to program. A classic Verilog example:
always @(posedge clk) begin
b <= a;
a <= b;
end
You know how SW developers like the teaser of swapping words... This is how HW people do it (and of course, if you had used a regular assignment "=" instead of the non-blocking one "<=", the swap would fail).