3 ms·

Okay? I'm asking because I don't know; can you elaborate on why that is? Aren't most modern GPUs similar in that they're designed to just shit out triangles a

by na85 8y ago

Okay? I'm asking because I don't know; can you elaborate on why that is? Aren't most modern GPUs similar in that they're designed to just shit out triangles as fast as possible, massively parallel?

chongli 8y ago
No, modern GPUs run many of the same instructions as CPUs. They have branches and everything. Their main limitation is that groups of threads are bundled together (called warps) and share a program counter, so lots of branching can result in a lot of wasted work if the threads disagree on which branch to take. That, and there's a huge penalty you pay for moving data across the bus to GPU RAM.
saagarjha 8y ago
Basically, you're going to try to emulate other instructions that you don't have with this one instruction, and that's not going to perform very well because now, instead of many optimized instructions, you have strings of this one instruction in its place. And I don't see any way to parallelize this: you're doing the same thing you always were, just with a bunch more code.
CyberDildonics 8y ago
Why would it make sense to use a single instruction? (Also no, GPUs are not the same at all)
stefs 8y ago
few problems are easily parallelizable. that said, that's not even the issue here. specialized instruction may be emulated by movs, but the speed loss could never be recouped even by massive parallelization.
- posterboy 8y ago
  The problem is probably the address space that movs use, instead of specialized registers with optimized pipelining. But internally, many instructions might actually come down to conditional moves. I guess that's either after the microcode is decoded, or if I guessed wrong about that, then Register Transfer Logik still pretty much sounds like it was based on, well, transfers.
uasm 8y ago
> "can you elaborate on why that is?" Might as-well suggest we use a single letter, instead of 26.
- Sohcahtoa82 8y ago
  .... --- .-- .- -... --- ..- - - .-- ---?
  - munk-a 8y ago
    ............... .............. ..... ............. ......... ....... ........ .................... ....................... ............... ................. ...........
- posterboy 8y ago
  ..... .. .. .. .. .. .. .. .. .... .. .. .. .. ..... .. .. The first number is zero, right? Then the first letter of the alphabet is well its hard to show because it doesn't print. It's just an empty set, nothing, a stop bit. We actually do use only 1 bit in digital cpus, but a weird mix of analogue in broad band transmission. I wonder why cpus don't use ternary or whatever. But I wonder why asynchronous CPUs didn't take off, so don't mind me, just being bored.

by na85 8y ago

Okay? I'm asking because I don't know; can you elaborate on why that is? Aren't most modern GPUs similar in that they're designed to just shit out triangles as fast as possible, massively parallel?

chongli 8y ago

No, modern GPUs run many of the same instructions as CPUs. They have branches and everything. Their main limitation is that groups of threads are bundled together (called warps) and share a program counter, so lots of branching can result in a lot of wasted work if the threads disagree on which branch to take. That, and there's a huge penalty you pay for moving data across the bus to GPU RAM.

saagarjha 8y ago

Basically, you're going to try to emulate other instructions that you don't have with this one instruction, and that's not going to perform very well because now, instead of many optimized instructions, you have strings of this one instruction in its place. And I don't see any way to parallelize this: you're doing the same thing you always were, just with a bunch more code.

CyberDildonics 8y ago

Why would it make sense to use a single instruction? (Also no, GPUs are not the same at all)

stefs 8y ago

few problems are easily parallelizable. that said, that's not even the issue here. specialized instruction may be emulated by movs, but the speed loss could never be recouped even by massive parallelization.

posterboy 8y ago
The problem is probably the address space that movs use, instead of specialized registers with optimized pipelining. But internally, many instructions might actually come down to conditional moves. I guess that's either after the microcode is decoded, or if I guessed wrong about that, then Register Transfer Logik still pretty much sounds like it was based on, well, transfers.

uasm 8y ago

> "can you elaborate on why that is?" Might as-well suggest we use a single letter, instead of 26.

Sohcahtoa82 8y ago
.... --- .-- .- -... --- ..- - - .-- ---?
- munk-a 8y ago
  ............... .............. ..... ............. ......... ....... ........ .................... ....................... ............... ................. ...........
posterboy 8y ago
..... .. .. .. .. .. .. .. .. .... .. .. .. .. ..... .. .. The first number is zero, right? Then the first letter of the alphabet is well its hard to show because it doesn't print. It's just an empty set, nothing, a stop bit. We actually do use only 1 bit in digital cpus, but a weird mix of analogue in broad band transmission. I wonder why cpus don't use ternary or whatever. But I wonder why asynchronous CPUs didn't take off, so don't mind me, just being bored.