3 ms·
If "tiring completeness" is supposed to read "Turing completeness", then including a conditional jump instruction of any sort completes the hardware requirement
by stan_rogers 8y ago
If "tiring completeness" is supposed to read "Turing completeness", then including a conditional jump instruction of any sort completes the hardware requirement. The rest is about the number of conditions upon which that may be based and the access semantics, and that's where the CISC, RISC and hybrid approaches differ.
- aswanson 8y agoAgreed. I'm just wondering if they followed some theoretical schema or just responded to evolutionary forces. Most likely the latter.
- deleted 8y ago[deleted]
- xenadu02 8y agoIt’s a direct evolution from 4004, 8008, 8080, to 8086. There was no compatibility but you can see the inspiration. IIRC 8086 was assembly compatible with 8080 but not binary compatible. At the time superscalar, register-renaming, vector-capable, and out-of-order were distant dreams and RAM was faster than the CPU. Everyone wrote assembly so the CPU designs accumulated instructions to make life easier on assembly programmers. 8086 was actually a stop-gap. The architecture astronauts at Intel that thought real hard about design were working on the iAPX 482, which was a stack machine that supported garbage collection in hardware(!)
- dboreham 8y ago432