Your implication that in the current Vega architecture a compute core can saturate the 1000GB/sec 4x1024bit RAM without some kind of segmentation is preposterou

Your implication that in the current Vega architecture a compute core can saturate the 1000GB/sec 4x1024bit RAM without some kind of segmentation is preposterous. We know there are 4 channels to switch between. So the idea that bandwidth "halves" with any intermediate step is clearly wrong since the bandwidth available to any compute core is already a fraction of the total available.