3 ms·

I'm also not sure why you're so focused on InifityFabric, it's a strawman. If Vega already has a 1000GB/sec bandwidth, what's stopping AMD from using that sa

I'm also not sure why you're so focused on InifityFabric, it's a strawman. If Vega already has a 1000GB/sec bandwidth, what's stopping AMD from using that same architecture to make an MMU on a smaller die to feed other small dies? InfinityFabric really has nothing to do with this, especially when locality has such a strong impact on possible bus-widths.

dragontamer 8y ago
How do you expect chiplets to connect to each other? HBM is the topology btw. Each 1024-bit connection (1024 pins!!) gives 250GB/s between the chip and RAM. 4-connections to RAM to one chip leads to 1000GB/s. With a chiplet design, you'd need 2 or more chips connected to RAM. The immediate design of 1-chip == 2 memory controllers + 1-chip == other two memory controllers (500GB/s per chip) now halves the bandwidth. So now you have to somehow, allow the two chips communicate at 500GB/s, bidirectional btw. (500GB/s from chip0 to chip1, and 500GB/s from chip1 to chip0). Even then, this bidirectional link will have horrible latency, since it will be Chip0 -> Chip1 -> HBM2 stack. So it just raises questions how anything would work at all. It just doesn't seem like an easy problem to solve to me. But hey, maybe I'm wrong and AMD got it figured out. All I'm saying is: no one has demonstrated a chip-to-chip bus that keeps up with HBM2 speeds.
- CoolGuySteve 8y ago
  Your implication that in the current Vega architecture a compute core can saturate the 1000GB/sec 4x1024bit RAM without some kind of segmentation is preposterous. We know there are 4 channels to switch between. So the idea that bandwidth "halves" with any intermediate step is clearly wrong since the bandwidth available to any compute core is already a fraction of the total available.
  - CoolGuySteve 8y ago
    SO IMPOSSIBLE https://www.pcgamesn.com/amd/amd-next-gen-graphics-card-architecture-arcturus https://www.pcgamesn.com/amd/amd-next-gen-graphics-card-arch...

dragontamer 8y ago

How do you expect chiplets to connect to each other? HBM is the topology btw. Each 1024-bit connection (1024 pins!!) gives 250GB/s between the chip and RAM. 4-connections to RAM to one chip leads to 1000GB/s. With a chiplet design, you'd need 2 or more chips connected to RAM. The immediate design of 1-chip == 2 memory controllers + 1-chip == other two memory controllers (500GB/s per chip) now halves the bandwidth. So now you have to somehow, allow the two chips communicate at 500GB/s, bidirectional btw. (500GB/s from chip0 to chip1, and 500GB/s from chip1 to chip0). Even then, this bidirectional link will have horrible latency, since it will be Chip0 -> Chip1 -> HBM2 stack. So it just raises questions how anything would work at all. It just doesn't seem like an easy problem to solve to me. But hey, maybe I'm wrong and AMD got it figured out. All I'm saying is: no one has demonstrated a chip-to-chip bus that keeps up with HBM2 speeds.

CoolGuySteve 8y ago
Your implication that in the current Vega architecture a compute core can saturate the 1000GB/sec 4x1024bit RAM without some kind of segmentation is preposterous. We know there are 4 channels to switch between. So the idea that bandwidth "halves" with any intermediate step is clearly wrong since the bandwidth available to any compute core is already a fraction of the total available.
- CoolGuySteve 8y ago
  SO IMPOSSIBLE https://www.pcgamesn.com/amd/amd-next-gen-graphics-card-architecture-arcturus https://www.pcgamesn.com/amd/amd-next-gen-graphics-card-arch...