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>NVidia doesn't have a scalar architecture in any meaningful sense of the word. CUDA threads are scalar, each CUDA core is a single scalar ALU, which CUDA core

>NVidia doesn't have a scalar architecture in any meaningful sense of the word. CUDA threads are scalar, each CUDA core is a single scalar ALU, which CUDA cores are assigned to a warp is flexible. >Nvidia literally cannot do async compute in the same way as AMD, because their micro-architecture cannot switch between graphics and compute on as finely grained a basis as GCN cards. Both AMD and NVIDIA GPUs have to do context switching. The difference is in scheduling GCN has a dedicate scheduler with 8 queues only for compute that is the ACE it sits utterly idle while doing graphics the graphics scheduler sits within each CU. >Nowhere in GCN are there any 4-wide SIMD arrays. Each CU contains an array of 4 SIMD units which each take a vec4 input, GCN is much closer to VILW4 than you think. Each CU also contains a scalar unit it cannot excute them in parallel. If the SIMD units cannot be fed they sit idle, idle CUDA cores can be assigned to a different warp. >Also nonsense. Both AMD and Nvidia have the majority of die space allocated to the compute cores ACE takes up about 15% of the die space that is big in my book.

dragontamer 8y ago
Unfortunately, I agree with the other poster. There are a number of inaccuracies in your post. > Each CU contains an array of 4 SIMD units which each take a vec4 input AMD SIMDs are (poorly named) scalar units, which are programmed using scalar arithmetic. FP16 is the only exception, as FP16 is a true SIMD operation (taking place inside a AMD scalar SIMD 2-at-a-time). Yeah, AMD really needed to name their stuff better. "vGPRs" ("vector General Purpose Registers") are in fact scalar units, as documented in the Vega Instruction Set. See chapter 6 for proof: https://developer.amd.com/wp-content/resources/Vega_Shader_ISA_28July2017.pdf https://developer.amd.com/wp-content/resources/Vega_Shader_I... The SIMDs replaced historical SIMD-units from the 6000-series roughly 10 years ago. I bet that the name is historical in nature. But AMD's cards are scalarly programmed, just like NVidia's. There is no need to use vec4 on modern (aka: anything in the last 10 years) cards from AMD. Half2 is the only thing that gets a benefit. > Each CU also contains a scalar unit it cannot excute them in parallel. The "Scalar" unit in AMD GPUs is... closer to a boolean-vector unit. AMD really chose bad names for these things... But anyway, it is a 64-bit unit, where each bit is used to calculate the execution masks to the vector units. The "Scalar" unit runs once every clock-tick. "Vector" units repeat themselves over 4-clock ticks (and therefore execute 4x slower than the Scalar unit). Ultimately, 1-Scalar unit can perform roughly the same amount of work as the 4-vector units. See page 31 for a great example on how the sALU of Vega is used to create loops and handle divergent cases. The "sALU" is effectively the unit to calculate "if" statements and "loops".
- atq2119 8y ago
  > The "Scalar" unit in AMD GPUs is... closer to a boolean-vector unit. AMD really chose bad names for these things... But anyway, it is a 64-bit unit, where each bit is used to calculate the execution masks to the vector units. This is a really cool way to put it, though I'd point out that the scalar unit is actually also used for (uniform) arithmetic, especially on pointers / indices. For example, if you have memory accesses of the form uniform_base + stride * thread_id, you can use the scalar ALU to compute / manipulate the uniform_base part. If you think of the GCN compute units as CPU cores with a really wide SIMD + powerful scatter/gather + texture sampling unit, the chosen terminology of scalar/vector ALUs makes sense. The difficulty is in mapping the (work item-centric) programming model that developers see to the hardware, but that's conceptually fairly similar to what ISPC does.
atq2119 8y ago
> idle CUDA cores can be assigned to a different warp. I have a feeling you're confusing lanes vs. cores here. Individual "threads" (work items) cannot migrate between warps, and every "core" only issues one instruction at a time (per execution port, in some of Nvidia's architectures). Each execution port is a SIMD execution port executing that instruction for multiple work items. If the work items of a warp diverge, some of the lanes of those SIMD execution units will be idle. This is the exact same behavior as on AMD's GCN, though obviously the terminology is different and some of the other details may be wired differently. > ACE takes up about 15% of the die space that is big in my book. I have a feeling that you're just making up numbers here. Can you point to evidence?

dragontamer 8y ago

Unfortunately, I agree with the other poster. There are a number of inaccuracies in your post. > Each CU contains an array of 4 SIMD units which each take a vec4 input AMD SIMDs are (poorly named) scalar units, which are programmed using scalar arithmetic. FP16 is the only exception, as FP16 is a true SIMD operation (taking place inside a AMD scalar SIMD 2-at-a-time). Yeah, AMD really needed to name their stuff better. "vGPRs" ("vector General Purpose Registers") are in fact scalar units, as documented in the Vega Instruction Set. See chapter 6 for proof: https://developer.amd.com/wp-content/resources/Vega_Shader_ISA_28July2017.pdf https://developer.amd.com/wp-content/resources/Vega_Shader_I... The SIMDs replaced historical SIMD-units from the 6000-series roughly 10 years ago. I bet that the name is historical in nature. But AMD's cards are scalarly programmed, just like NVidia's. There is no need to use vec4 on modern (aka: anything in the last 10 years) cards from AMD. Half2 is the only thing that gets a benefit. > Each CU also contains a scalar unit it cannot excute them in parallel. The "Scalar" unit in AMD GPUs is... closer to a boolean-vector unit. AMD really chose bad names for these things... But anyway, it is a 64-bit unit, where each bit is used to calculate the execution masks to the vector units. The "Scalar" unit runs once every clock-tick. "Vector" units repeat themselves over 4-clock ticks (and therefore execute 4x slower than the Scalar unit). Ultimately, 1-Scalar unit can perform roughly the same amount of work as the 4-vector units. See page 31 for a great example on how the sALU of Vega is used to create loops and handle divergent cases. The "sALU" is effectively the unit to calculate "if" statements and "loops".

atq2119 8y ago
> The "Scalar" unit in AMD GPUs is... closer to a boolean-vector unit. AMD really chose bad names for these things... But anyway, it is a 64-bit unit, where each bit is used to calculate the execution masks to the vector units. This is a really cool way to put it, though I'd point out that the scalar unit is actually also used for (uniform) arithmetic, especially on pointers / indices. For example, if you have memory accesses of the form uniform_base + stride * thread_id, you can use the scalar ALU to compute / manipulate the uniform_base part. If you think of the GCN compute units as CPU cores with a really wide SIMD + powerful scatter/gather + texture sampling unit, the chosen terminology of scalar/vector ALUs makes sense. The difficulty is in mapping the (work item-centric) programming model that developers see to the hardware, but that's conceptually fairly similar to what ISPC does.

atq2119 8y ago

> idle CUDA cores can be assigned to a different warp. I have a feeling you're confusing lanes vs. cores here. Individual "threads" (work items) cannot migrate between warps, and every "core" only issues one instruction at a time (per execution port, in some of Nvidia's architectures). Each execution port is a SIMD execution port executing that instruction for multiple work items. If the work items of a warp diverge, some of the lanes of those SIMD execution units will be idle. This is the exact same behavior as on AMD's GCN, though obviously the terminology is different and some of the other details may be wired differently. > ACE takes up about 15% of the die space that is big in my book. I have a feeling that you're just making up numbers here. Can you point to evidence?