EDIT: I got some stuff mixed up. This post is all wrong. It's supposedly one IO fits all. It has to interconnect up to 8 CPU chips and 4-8 memory channels (and

EDIT: I got some stuff mixed up. This post is all wrong. It's supposedly one IO fits all. It has to interconnect up to 8 CPU chips and 4-8 memory channels (and allegedly some L4 cache). It has to support 128 PCIe lanes (maybe more for the upcoming generation) too. Then also, it's 14nm, so things aren't as small. I imagine that they laser out most of the die to save power on consumer chips.