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> A "RISC 6502" likely wasn't a "reduced instruction set 6502" it was more likely a "non-microcoded single cycle CPU running the 6502 instruction set" The 6502
by zozbot123 8y ago
> A "RISC 6502" likely wasn't a "reduced instruction set 6502" it was more likely a "non-microcoded single cycle CPU running the 6502 instruction set"
The 6502 was not microcoded. It used simple wired logic (implemented in a PLA) to "decode" and "run" opcodes by driving other parts of the chip. This is why many unimplemented opcodes "work", sometimes with recognizable effects.
- Taniwha 8y agoUsing a PLA vs microcode to sequence a multiple clock instruction execution is sort of a no-op (ie they're pretty much the same thing) when comparing how a CISCy chip works compared with a RISC which has instructions designed to be easily decoded by random logic and executed in one clock
- zozbot123 8y agoThe 6502 and Z80 were both 'CISCy' chips, but they were very different when it came to instruction execution. While formally a PLA may have been used to "sequence a multiple-clock instruction" in both, in a practical sense 6502 instructions took a handful of clock cycles to execute, not very dissimilar from later RISC chips. I think your point is more valid for the Z80 than for the 6502.
- Taniwha 8y agoyes but RISC at the time was all about throwing that stuff away and executing a single instruction per clock (with an actual pipeline, something those early microprocessors didn't have) the result were much faster CPU's that ran essentially one clock and one instructions per L1 cache cycle, rather than one clock per main memory cycle (and each instruction being many memory cycles) - ie 20-50MHz rather than 1MHz - remember 6502s and their ilk ran unrolled pipelines visible on the main memory bus