They're learning a subset of Verilog which excludes test benches, which is a huge amount of a project (by code and by time) and is introduced in every single be

They're learning a subset of Verilog which excludes test benches, which is a huge amount of a project (by code and by time) and is introduced in every single beginner HDL text. You'll probably be in Chapter 3 of most books when this simulator fails you in a way you can't figure out; I think this is pedagogically unsound to say it is good for newcomers. If they started with a low cost FPGA board and XSim, they could practically use everything they'd learned.