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I don't know that it's hyperbole - Verilator is a huge leap for a newcomer. We're going to take someone who is just getting into Verilog, and add C/C++, makefil
by analognoise 8y ago
I don't know that it's hyperbole - Verilator is a huge leap for a newcomer. We're going to take someone who is just getting into Verilog, and add C/C++, makefiles, then we're going to add the problems you've got with a cycle simulator (testbench code won't work) - we have to explain what a delta cycle is, and the most popular tutorials online (ZipCPU's Verilator blogs) mention using a delta-cycle simulator (like Icarus) just to check that you're getting what you expect.
It's frustrating that people keep suggesting FOSS tools when they're either orders of magnitude more complex, not very good in a huge number of cases, require an experienced engineer to actually use, and can't simulate simple Xilinx IP.
People think they're familiar with it because they looked up "FOSS Verilog Simulator" once because they were curious, but they can't actually tell you about these things. We should direct newcomers to Xilinx Vivado, getting started with ISim, and if they're far more sophisticated and have a handle on the language already, then move them to Verilator in certain cases.
But starting with Verilator would be like saying, "Just write a C compiler in assembly, then start using that C compiler." - Nobody starts there!
- microcolonel 8y agoThe first time I tried to set up Xilinx Vivado, Xilinx swallowed my license and didn't provide a board definition for my Zynq (for which the license applied); when I tried contacting them, they couldn't help me work it out. Maybe it's possible to direct newcomers to Xilinx Vivado, and I agree that they're more likely to be productive that way, but there's also a good chance their investment will go up in smoke and they will have no way to debug that. It's not as though the thing is "easier" in every way than using any of the public simulation tools, and it sure as hell costs more when it goes wrong.
- analognoise 8y agoBoard definition files don't do a license check, only bitstream generation does - so it wasn't a license issue. But let's examine this more closely: https://www.xilinx.com/products/design-tools/vivado/vivado-webpack.html#architecture https://www.xilinx.com/products/design-tools/vivado/vivado-w... The largest supported Zynq-7000 with the (free) Webpack is the XC7Z030. The $900 ZC702 has a XC7Z020 on it, which is a Webpack part (no part license needed), so you probably bought the $2500 ZC706 (which contains a XC7Z045 part)? So you bought a ~$2500 board, and the license was successfully applied, but you couldn't get the board definition file to work (a part that has no license checks...) now you're claiming that the investment would be "up in smoke" for a newcomer? Honestly this sounds like user error; Create New Project -> Enter name and location of Project -> Type of Project (Select RTL, fine) -> Click on BOARDS and select your board -> Finish. Now when you use something like IP Integrator, the board presets should be available. If you're still having trouble with it, I can walk you through it with screenshots if you'd like, but there are also tutorials and videos from Xilinx that go over "Creating your first project", they're a great way to get started; try this: ZC706 Getting Started Guide (includes screenshots of not only the hardware, but every step): https://www.xilinx.com/support/documentation/boards_and_kits/zc706/2014_4/ug961-zc706-GSG.pdf https://www.xilinx.com/support/documentation/boards_and_kits...