4 ms·

Is it possible to hack the microcode so that it can run ARM assembly natively?

bayindirh 8y ago
It would be hard, because the ISA is tightly bound to the underlying silicon's structure. Some of the commands cannot be translated to the silicon effectively or not at all. e.g.: MIPS have 64 x 64bit registers. You can use any of them as a source or a destination, however x86 always designates EAX as the ALU accumulator. This has some profound effects on silicon design.
- gpderetta 8y ago
  > x86 always designates EAX as the ALU accumulat Actually no. After decoding there is nothing special in the aex register. AMD at some point was going to release K10 which was basically Zen but with an ARM decoder. It got cancelled when Zen proved viable and AMD decided it was better to compete with Intel than all the ARM vendors.
  - floatboth 8y ago
    https://softiron.com/development-tools/overdrive-1000/ https://softiron.com/development-tools/overdrive-1000/ They actually "released" (to one manufacturer it seems) the Opteron A1100. With stock Cortex-A57 cores, not "Zen with an ARM decoder".
  - bayindirh 8y ago
    > Actually no. After decoding there is nothing special in the aex register. The microcode, or specifically the modern x86 processors, are using register renaming to move things around, but the actual ASM commands imply that the results should end in EAX register. You cannot arbitrarily do a MUL and get the result from EBX for example [3]. i.e. x86 assembly dictates where the results should end in. AMD played with two ideas: A pure ARM core, and a hybrid x86 core with ARM co-processor. The ARM core missed the performance targets [0], and they also abandoned the ARM accelerated x86 core [1], but I don't know why. They never intended to go full TransMeta and transcode the x86 ASM into something proprietary or ARM. Bonus: It seems they are still muling the idea of X86/ARM hybrid [2]. [0]: https://www.theregister.co.uk/2018/11/27/amazon_aws_graviton_specs/ https://www.theregister.co.uk/2018/11/27/amazon_aws_graviton... [1]: https://www.extremetech.com/computing/205078-amds-project-skybridge-the-armx86-hybrid-core-is-officially-dead https://www.extremetech.com/computing/205078-amds-project-sk... [2]: https://www.reddit.com/r/AMD_Stock/comments/8x4sba/the_return_of_the_x86arm_hybrid/ https://www.reddit.com/r/AMD_Stock/comments/8x4sba/the_retur... [3]: https://c9x.me/x86/html/file_module_x86_id_210.html https://c9x.me/x86/html/file_module_x86_id_210.html
monocasa 8y ago
Nope. The chip is very much designed around x86 decoding, even before you get to the ucode ROM/RAM. Additionally, you only have a handful of patch RAM locations.
pkaye 8y ago
The instruction decoder that breaks up the variable length instruction set into micro-ops is likely hard coded.

It would be hard, because the ISA is tightly bound to the underlying silicon's structure. Some of the commands cannot be translated to the silicon effectively or not at all. e.g.: MIPS have 64 x 64bit registers. You can use any of them as a source or a destination, however x86 always designates EAX as the ALU accumulator. This has some profound effects on silicon design.

gpderetta 8y ago
> x86 always designates EAX as the ALU accumulat Actually no. After decoding there is nothing special in the aex register. AMD at some point was going to release K10 which was basically Zen but with an ARM decoder. It got cancelled when Zen proved viable and AMD decided it was better to compete with Intel than all the ARM vendors.
- floatboth 8y ago
  https://softiron.com/development-tools/overdrive-1000/ https://softiron.com/development-tools/overdrive-1000/ They actually "released" (to one manufacturer it seems) the Opteron A1100. With stock Cortex-A57 cores, not "Zen with an ARM decoder".
- bayindirh 8y ago
  > Actually no. After decoding there is nothing special in the aex register. The microcode, or specifically the modern x86 processors, are using register renaming to move things around, but the actual ASM commands imply that the results should end in EAX register. You cannot arbitrarily do a MUL and get the result from EBX for example [3]. i.e. x86 assembly dictates where the results should end in. AMD played with two ideas: A pure ARM core, and a hybrid x86 core with ARM co-processor. The ARM core missed the performance targets [0], and they also abandoned the ARM accelerated x86 core [1], but I don't know why. They never intended to go full TransMeta and transcode the x86 ASM into something proprietary or ARM. Bonus: It seems they are still muling the idea of X86/ARM hybrid [2]. [0]: https://www.theregister.co.uk/2018/11/27/amazon_aws_graviton_specs/ https://www.theregister.co.uk/2018/11/27/amazon_aws_graviton... [1]: https://www.extremetech.com/computing/205078-amds-project-skybridge-the-armx86-hybrid-core-is-officially-dead https://www.extremetech.com/computing/205078-amds-project-sk... [2]: https://www.reddit.com/r/AMD_Stock/comments/8x4sba/the_return_of_the_x86arm_hybrid/ https://www.reddit.com/r/AMD_Stock/comments/8x4sba/the_retur... [3]: https://c9x.me/x86/html/file_module_x86_id_210.html https://c9x.me/x86/html/file_module_x86_id_210.html

monocasa 8y ago

Nope. The chip is very much designed around x86 decoding, even before you get to the ucode ROM/RAM. Additionally, you only have a handful of patch RAM locations.

pkaye 8y ago

The instruction decoder that breaks up the variable length instruction set into micro-ops is likely hard coded.