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That's a really good question and I hope someone comes by to answer it. My guess is that people go beyond this and already design entire adders and stuff at th
by marvy 8y ago
That's a really good question and I hope someone comes by to answer it. My guess is that people go beyond this and already design entire adders and stuff at the transistor level if they think it affects their bottleneck.
- akiselev 8y agoI'm not a silicon engineer (I just pretend to be one to get my vendors to skip me right to their engineers for support) but afaik, Intel has been using weird phenomenon in semiconductors for useful work for a decade at a "lower level" than the logic gates. It's why they've managed to stay ahead of competition even on equivalent nodes and also why they've dug themselves into a corner (since they cant decouple their fab from IC design to spin off a TSMC competitor). Their cell library is likely the most specialized on the planet. I've also heard whispers that the Movidius Myriad II (company later acquired by Intel) actually used some sort of monte carlo optimization simulations to design pieces of the chip. Instead of optimizing some of the more specialized computer/stereo vision algorithms themselves, they threw the testbench at a really complicated constraint solver/optimizer and it spit out designs based on physical simulations where the individual units looked nothing like the logic gates used by a human designer and far more like an analog circuit using semiconductors.
- yazaddaruvala 8y agoOh that’s cool! I had read about simulated annealing being used to optimize FPGA logic unit layouts. I assumed something similar was used to optimize gate layouts but never thought about actually optimizing the transistor layouts independent of NAND. That sounds like a great idea!