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I’m curious, have we moved passed NAND gate only ICs? Given that it takes many NAND gates to be logically equivalent to the rest of logic, wouldn’t creating OR

I’m curious, have we moved passed NAND gate only ICs? Given that it takes many NAND gates to be logically equivalent to the rest of logic, wouldn’t creating OR and AND gates directly reduce the number of transistors and therefore help Moore’s Law as well?

marvy 8y ago
That's a really good question and I hope someone comes by to answer it. My guess is that people go beyond this and already design entire adders and stuff at the transistor level if they think it affects their bottleneck.
- akiselev 8y ago
  I'm not a silicon engineer (I just pretend to be one to get my vendors to skip me right to their engineers for support) but afaik, Intel has been using weird phenomenon in semiconductors for useful work for a decade at a "lower level" than the logic gates. It's why they've managed to stay ahead of competition even on equivalent nodes and also why they've dug themselves into a corner (since they cant decouple their fab from IC design to spin off a TSMC competitor). Their cell library is likely the most specialized on the planet. I've also heard whispers that the Movidius Myriad II (company later acquired by Intel) actually used some sort of monte carlo optimization simulations to design pieces of the chip. Instead of optimizing some of the more specialized computer/stereo vision algorithms themselves, they threw the testbench at a really complicated constraint solver/optimizer and it spit out designs based on physical simulations where the individual units looked nothing like the logic gates used by a human designer and far more like an analog circuit using semiconductors.
  - yazaddaruvala 8y ago
    Oh that’s cool! I had read about simulated annealing being used to optimize FPGA logic unit layouts. I assumed something similar was used to optimize gate layouts but never thought about actually optimizing the transistor layouts independent of NAND. That sounds like a great idea!
atq2119 8y ago
NOR gates are actually commonly used, as are AOIs/OAIs in many technologies (and or inverters, 3-input circuits that are common in adders). OR and AND cannot be built directly in CMOS technology. The most efficient way to build them is by combining a NOR/NAND with an inverter. Edit: To clarify, I believe there are cell libraries that do have OR and AND, but the transistor count is the same as NOR/NAND + inverter, so it's a bit questionable whether there's really an advantage to using them.
deleted 8y ago
[deleted]
twtw 8y ago
> wouldn’t creating OR and AND gates directly reduce the number of transistors No. Gates require varying numbers of transistors to implement in CMOS. This idea is almost exactly backwards - logic is reduced to nand because nand requires the fewest transistors, not because CMOS can't (or couldn't) make anything else.
zozbot123 8y ago
There is no need to have "NAND gate only" ICs in CMOS. You can easily implement any AND-OR-only network followed by an invert (NOT) gate for the output. As a further example, pass transistor logic is an alternative which can be implemented using CMOS transmission gates, it does not use a NOT stage however this means that it will not restore the signal voltage for the next stage, unlike the usual sort of CMOS logic.
Taniwha 8y ago
we often use 'nand-gates' as a metric - in cmos they're about the smallest useful gate (other than an inverter) you can make - (4 transistors) - it doesn't mean we build everything from nand-gates - in fact a std cell library usually has 30-100 gates in it and synthesis tools pick the right gates for the job as we compile up our chips

marvy 8y ago

That's a really good question and I hope someone comes by to answer it. My guess is that people go beyond this and already design entire adders and stuff at the transistor level if they think it affects their bottleneck.

akiselev 8y ago
I'm not a silicon engineer (I just pretend to be one to get my vendors to skip me right to their engineers for support) but afaik, Intel has been using weird phenomenon in semiconductors for useful work for a decade at a "lower level" than the logic gates. It's why they've managed to stay ahead of competition even on equivalent nodes and also why they've dug themselves into a corner (since they cant decouple their fab from IC design to spin off a TSMC competitor). Their cell library is likely the most specialized on the planet. I've also heard whispers that the Movidius Myriad II (company later acquired by Intel) actually used some sort of monte carlo optimization simulations to design pieces of the chip. Instead of optimizing some of the more specialized computer/stereo vision algorithms themselves, they threw the testbench at a really complicated constraint solver/optimizer and it spit out designs based on physical simulations where the individual units looked nothing like the logic gates used by a human designer and far more like an analog circuit using semiconductors.
- yazaddaruvala 8y ago
  Oh that’s cool! I had read about simulated annealing being used to optimize FPGA logic unit layouts. I assumed something similar was used to optimize gate layouts but never thought about actually optimizing the transistor layouts independent of NAND. That sounds like a great idea!

atq2119 8y ago

NOR gates are actually commonly used, as are AOIs/OAIs in many technologies (and or inverters, 3-input circuits that are common in adders). OR and AND cannot be built directly in CMOS technology. The most efficient way to build them is by combining a NOR/NAND with an inverter. Edit: To clarify, I believe there are cell libraries that do have OR and AND, but the transistor count is the same as NOR/NAND + inverter, so it's a bit questionable whether there's really an advantage to using them.

deleted 8y ago

[deleted]

twtw 8y ago

> wouldn’t creating OR and AND gates directly reduce the number of transistors No. Gates require varying numbers of transistors to implement in CMOS. This idea is almost exactly backwards - logic is reduced to nand because nand requires the fewest transistors, not because CMOS can't (or couldn't) make anything else.

zozbot123 8y ago

There is no need to have "NAND gate only" ICs in CMOS. You can easily implement any AND-OR-only network followed by an invert (NOT) gate for the output. As a further example, pass transistor logic is an alternative which can be implemented using CMOS transmission gates, it does not use a NOT stage however this means that it will not restore the signal voltage for the next stage, unlike the usual sort of CMOS logic.

Taniwha 8y ago

we often use 'nand-gates' as a metric - in cmos they're about the smallest useful gate (other than an inverter) you can make - (4 transistors) - it doesn't mean we build everything from nand-gates - in fact a std cell library usually has 30-100 gates in it and synthesis tools pick the right gates for the job as we compile up our chips