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Yeah. Frequency is higher, but not sure if you can overclock it. The biggest problem I saw on these EPYC chips (potentially) is that the PCIe lanes spread acros
by liuliu 8y ago
Yeah. Frequency is higher, but not sure if you can overclock it. The biggest problem I saw on these EPYC chips (potentially) is that the PCIe lanes spread across 4 dies. So the performance of data going through host would be interesting to observe. This is a setup with some risks, so would like to hear more from the crowd the feasibility.
- ericd 8y agoAh yeah, the higher die count TR's had some interesting performance characteristics, according to Anandtech. One surprising result was that the inter-die communication silicon used more power than the cores themselves sometimes, IIRC. I'd probably check out that article, since I'm guessing some of it applies to the similar core-count Epycs.