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Speaking about design challenges - it would be nice if industry will switch to LLVM-like low-level HDL (or RTL) language, that will allow easier cross-tool inte
by xvilka 8y ago
Speaking about design challenges - it would be nice if industry will switch to LLVM-like low-level HDL (or RTL) language, that will allow easier cross-tool integration. So far every project implements everything itself. There is an idea[1] to adapt FIRRTL[2][3] for this needs. Here is a good paper[4] describing its features. Apparently Intel also using it, at least in the research labs. This will help to integrate all parts of FPGA and ASIC design pipeline together. For now chip-design feels like programming in 1990 - quality of tooling is very bad.
[1] https://github.com/SymbiFlow/ideas/issues/19 https://github.com/SymbiFlow/ideas/issues/19
[2] https://bar.eecs.berkeley.edu/projects/firrtl.html https://bar.eecs.berkeley.edu/projects/firrtl.html
[3] https://github.com/freechipsproject/FIRRTL https://github.com/freechipsproject/FIRRTL
[4] https://aspire.eecs.berkeley.edu/wp/wp-content/uploads/2017/11/Reusability-is-FIRRTL-Ground-Izraelevitz.pdf https://aspire.eecs.berkeley.edu/wp/wp-content/uploads/2017/...
- posterboy 8y agoFor what it's worth, most stuff designed that way could be from the 80s. Only now it's cheaper and smaller. I mean NES emulators, 10MHz 8080 clones.
- buckysock 8y agoIt will stay like this for the foreseeable future. Chip design IP is too obscure for the mainstream oss people to force an oss ecosystem. There’s also too much proprietary foundry information needed to even have an oss ecosystem that actually works properly. Ironically the closedness of chip design tools and foundry information is also what prevents it from truly growing. Entrenched players (cad companies) benefit from this, but the losers are the actual chip design companies. They are bleeding generation of engineers who have forsaken this climate for the more cozy cs oss climate.