4 ms·

Without expensive Xilinx IP to drive tandem configuration over PCIe, how is this useful for development when installed in a laptop (or any enclosed device witho

Without expensive Xilinx IP to drive tandem configuration over PCIe, how is this useful for development when installed in a laptop (or any enclosed device without direct access to JTAG TAP)? LitePCIe[1] was briefly mentioned, but I don't see how this addresses the issue. Also, the mandatory heatsink for "heavy designs" (without any notion of what that means) is a bit...limiting. [1] https://github.com/enjoy-digital/litepcie https://github.com/enjoy-digital/litepcie

walterbell 8y ago
Vivado and Artix-7 include a hard IP block [1] for PCIe Gen2, with Linux and Windows drivers. A similar device, https://picoevb.com https://picoevb.com, has a virtual JTAG cable. [1] http://xilinx.eetrend.com/files-eetrend-xilinx/download/201303/3844-7699-yongsailingsi7xiliefpgashejiqianrushipciemokuai.pdf http://xilinx.eetrend.com/files-eetrend-xilinx/download/2013...
- CamperBob2 8y ago
  That IP block is only used to talk to the PHY, in this case the high-speed transceiver hardware built into the 7-series FPGAs. You still have to license some (very) non-free IP from a vendor like Northwest Logic or Xillybus if you don't want to take on a major R&D project to get PCIe up and running. Then there's the question of driver licensing on the OS side, if you want Windows support. Not sure if there are any prepackaged free-as-in-beer solutions for that. There were none when I looked into it a few years ago.
  - walterbell 8y ago
    UCSD's RIFFA [1][2] open-source PCIe framework includes Windows 7 & Linux drivers and their 2015 paper [3] claims support for Xilinx 7-series FPGAs. [1] https://forums.xilinx.com/t5/Xcell-Daily-Blog-Archived/Need-fast-efficient-open-source-PCIe-DMA-for-your-FPGA-RIFFA-2-2/ba-p/642947 https://forums.xilinx.com/t5/Xcell-Daily-Blog-Archived/Need-... [2] https://github.com/KastnerRG/riffa https://github.com/KastnerRG/riffa > RIFFA (Reusable Integration Framework for FPGA Accelerators) is a simple framework for communicating data from a host CPU to a FPGA via a PCI Express bus. The framework requires a PCIe enabled workstation and a FPGA on a board with a PCIe connector. RIFFA supports Windows and Linux, Altera and Xilinx, with bindings for C/C++, Python, MATLAB and Java .. Users can communicate with FPGA IP cores by writing only a few lines of code ... No knowledge of bus addresses, buffer sizes, or PCIe packet formats is required. Simply send data on a FIFO interface and receive data on a FIFO interface. RIFFA does not rely on a PCIe Bridge and therefore is not subject to the limitations of a bridge implementation. Instead, RIFFA works directly with the PCIe Endpoint and can run fast enough to saturate the PCIe link. [3] https://87c7e184-a-d06fb7e1-s-sites.googlegroups.com/a/eng.ucsd.edu/matt-jacobsen/06645504.pdf https://87c7e184-a-d06fb7e1-s-sites.googlegroups.com/a/eng.u...
    - CamperBob2 8y ago
      Hmm, that looks really cool, thanks. It definitely wasn't around when I needed it, and I'm surprised not to have heard of it in the meantime. Seems like a legitimate end-to-end solution.
deleted 8y ago
[deleted]

walterbell 8y ago

Vivado and Artix-7 include a hard IP block [1] for PCIe Gen2, with Linux and Windows drivers. A similar device, https://picoevb.com https://picoevb.com, has a virtual JTAG cable. [1] http://xilinx.eetrend.com/files-eetrend-xilinx/download/201303/3844-7699-yongsailingsi7xiliefpgashejiqianrushipciemokuai.pdf http://xilinx.eetrend.com/files-eetrend-xilinx/download/2013...

CamperBob2 8y ago
That IP block is only used to talk to the PHY, in this case the high-speed transceiver hardware built into the 7-series FPGAs. You still have to license some (very) non-free IP from a vendor like Northwest Logic or Xillybus if you don't want to take on a major R&D project to get PCIe up and running. Then there's the question of driver licensing on the OS side, if you want Windows support. Not sure if there are any prepackaged free-as-in-beer solutions for that. There were none when I looked into it a few years ago.
- walterbell 8y ago
  UCSD's RIFFA [1][2] open-source PCIe framework includes Windows 7 & Linux drivers and their 2015 paper [3] claims support for Xilinx 7-series FPGAs. [1] https://forums.xilinx.com/t5/Xcell-Daily-Blog-Archived/Need-fast-efficient-open-source-PCIe-DMA-for-your-FPGA-RIFFA-2-2/ba-p/642947 https://forums.xilinx.com/t5/Xcell-Daily-Blog-Archived/Need-... [2] https://github.com/KastnerRG/riffa https://github.com/KastnerRG/riffa > RIFFA (Reusable Integration Framework for FPGA Accelerators) is a simple framework for communicating data from a host CPU to a FPGA via a PCI Express bus. The framework requires a PCIe enabled workstation and a FPGA on a board with a PCIe connector. RIFFA supports Windows and Linux, Altera and Xilinx, with bindings for C/C++, Python, MATLAB and Java .. Users can communicate with FPGA IP cores by writing only a few lines of code ... No knowledge of bus addresses, buffer sizes, or PCIe packet formats is required. Simply send data on a FIFO interface and receive data on a FIFO interface. RIFFA does not rely on a PCIe Bridge and therefore is not subject to the limitations of a bridge implementation. Instead, RIFFA works directly with the PCIe Endpoint and can run fast enough to saturate the PCIe link. [3] https://87c7e184-a-d06fb7e1-s-sites.googlegroups.com/a/eng.ucsd.edu/matt-jacobsen/06645504.pdf https://87c7e184-a-d06fb7e1-s-sites.googlegroups.com/a/eng.u...
  - CamperBob2 8y ago
    Hmm, that looks really cool, thanks. It definitely wasn't around when I needed it, and I'm surprised not to have heard of it in the meantime. Seems like a legitimate end-to-end solution.

deleted 8y ago

[deleted]