4 ms·
This is awesome! It might mean we get a CHERI board without a RISC-V port. The port is still a good idea but a port to highest-end MIPS will probably be cheaper
by nickpsecurity 8y ago
This is awesome! It might mean we get a CHERI board without a RISC-V port. The port is still a good idea but a port to highest-end MIPS will probably be cheaper since it reuses toolchain and some hardware stuff.
Then we can make the desktop cases look like SGI’s as a tribute to the best MIPS of the past. Plus, they look cool.
https://www.cl.cam.ac.uk/research/security/ctsrd/cheri/ https://www.cl.cam.ac.uk/research/security/ctsrd/cheri/
- walterbell 8y agoThat would be industry-changing for desktop security - capabilities in open hardware. Does the MIPS ecosystem have an equivalent to coreboot?
- LargoLasskhyfv 8y agoFor what? There is https://en.wikipedia.org/wiki/Das_U-Boot https://en.wikipedia.org/wiki/Das_U-Boot and https://www.linux-mips.org/wiki/PMON_2000 https://www.linux-mips.org/wiki/PMON_2000 I bet "Das U-Boot" is more of an "ecosystem" than coreboot when you zoom far out and see the installed base of embedded devices. Coreboot unfortunately not so much in comparison.
- pjmlp 8y agoCurrently I am looking into the Arm v8.3+ memory tagging instructions. It still isn't SPARC ADI, but at least we might get some additional safety along the OS stack that way.