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MIPS was on its way to irrelevance, first as ARM slowly ate its remaining marketshare, then quickly when Imagination Technology went under and sold it off for a
by ac29 8y ago
MIPS was on its way to irrelevance, first as ARM slowly ate its remaining marketshare, then quickly when Imagination Technology went under and sold it off for a pittance to a relatively obscure "AI" company.
RISC-V may have hastened its demise, but the writing was on the wall for a long time.
- chasil 8y agoI don't program in assembler professionally, but I understand that MIPS has some ugly, ugly aspects: https://www.jwhitham.org/2016/02/risc-instruction-sets-i-have-known-and.html https://www.jwhitham.org/2016/02/risc-instruction-sets-i-hav... Sun opened the SPARC T2 a decade ago, and it certainly has not become popular: https://www.oracle.com/technetwork/systems/opensparc/opensparc-t2-page-1446157.html https://www.oracle.com/technetwork/systems/opensparc/openspa... It does seem that RISC-V corrects a number of these design eccentricities. SPARC did not move the market an inch with an open release - perhaps MIPS will fail just as spectacularly.
- walterbell 8y agoThere are large numbers of consumer MIPS devices (routers) in existence, which run mature open-source software stacks. Future iterations of MIPS can be governed by a multi-stakeholder community, avoiding past mistakes and designing for future requirements, including AI/ML and other domain-specific use cases.
- snaky 8y agoAh, those mature MIPS routers https://news.ycombinator.com/item?id=18688947 https://news.ycombinator.com/item?id=18688947
- walterbell 8y agoYep :) They can be fixed with a software update.
- rasz 8y agoCan, but wont.
- bcaa7f3a8bbc 8y agoMIPS is mature, all the toolchains are here. It's simply that most vendors are too incompetent to care, as it doesn't affect their revenue in any way. > Security and Hardening by Steven Barth - OpenWrt Summit > Introducing new and ongoing security improvements to bleeding edge OpenWrt. This talk describes the new default toolchain featuring musl libc, enabled hardening including ASLR, SSP as well as OpenWrt's novel jailing (jailfs and seccomp) and package signing features (based on Curve25519). > https://www.youtube.com/watch?v=DNYvIrI5Bbs https://www.youtube.com/watch?v=DNYvIrI5Bbs On the other hand, OpenWrt implemented full system-wide ASLR recently. NX and jailfs is still a WIP.
- gumby 8y agoMIPS support is some of the most mature in GCC. The architecture is well understood.
- rurban 8y agoNot really. It's still by far the sanest and easiest of all assembly ISA's. And cheap. SPARC is beyond crazy (esp. with its delays), ARM hopelessly balkanized, Intel more than crazy, RISC-V immature. POWER is the only other pretty good assembly ISA, but too expensive. The worst MIPS problem is the softfloat compiler crazyness (executable stack), but that's a gcc/binutils sin from a decade ago.
- wbl 8y agoRegister windows were copied by MMIX.
- floatboth 8y ago> ARM hopelessly balkanized ???
- deaddodo 8y agoI'm curious in what way you find ARM balkanized? It's all AArch32 + some variety of soft/hard-float or AArch64 with standardized NEON. In fact, the architecture/ISA is the one thing that is sane about ARM; since Nvidia, Samsung, Qualcomm, Apple, Applied, Cavium, etc all have vastly different use-cases and goals for ARM.
- spoonhat 8y agoThe blog post you link to criticizes MIPS because it has pipeline hazards and branch delay slots. MIPS had hazards in 1985. MIPS II eliminated hazards. No MIPS processor released after 1989 has hazards. Branch delay slots are no big deal once you know they're there. There are a number of equally questionable design decisions in RISC-V, such as variable length instruction encoding and dest, src order of instruction operands. But RISC-V does have momentum.
- amluto 8y ago> Branch delay slots are no big deal once you know they're there. I disagree. I'm not really a MIPS user, but I've managed to encounter some branch delay slot issues, and, as an x86 system programmer, I can only imagine how unpleasant they must be. Here are some reasons: - The program counter does not adequately describe the execution state of the CPU. In other words, starting or resuming execution with a given set of register values and a given address will do the wrong thing if you're resuming in a branch delay slot. - Handling a fault due to an instruction in a branch delay slot seems highly problematic. Suppose you have a load in a delay slot and the load touches swapped-out memory. How is the operating system supposed to page in that memory and resume? - Linux, and probably other operating systems, will emulate FPU instructions if the CPU doesn't support them. Emulating FPU branch instructions is deeply problematic because of delay slots.
- monocasa 8y agoThe first two just mean that there's an extra trap state bit in a flags register for "I'm in a bench delay slot currently" and isn't really a big deal. The third one I imagine is a pain in the ass, but I've been lucky enough to always compile MIPS for the exact CPU I was running it on.
- amluto 8y agoIt’s more than just a bit. You need a bit saying “in a delay slot” and a whole word that stores the target of the branch.
- ineedasername 8y agoSun opened the SPARC T2 a decade ago, and it certainly has not become popular I'm not saying it would have become any more popular without this, but the fact that Oracle purchased Sun probably didn't help adoption here, at all.
- pjmlp 8y agoWhich is a pity, as currently the SPARC is the only commercial CPU able to tame C. At least with luck those features are coming to ARM v8.3+ as well.
- masklinn 8y ago> Which is a pity, as currently the SPARC is the only commercial CPU able to tame C. What do you mean? That it includes protection modes which make C "safe"?
- kazinator 8y agoSPARC has weird register windows that scare C programmers out of playing games with the stack, resulting in safer operation.
- pjmlp 8y agoSPARC ADI is a bit more than that.
- pjmlp 8y agoSPARC has memory tagging support since M7. https://swisdev.oracle.com/_files/What-Is-ADI.html https://swisdev.oracle.com/_files/What-Is-ADI.html https://swisdev.oracle.com/_files/M7_Preso.pdf https://swisdev.oracle.com/_files/M7_Preso.pdf This is enabled by default in Solaris since version 11. "Secure Software - Made Simple with Software in Silicon" https://www.youtube.com/watch?v=krOhcjF5Fsw https://www.youtube.com/watch?v=krOhcjF5Fsw https://lazytyped.blogspot.com/2016/12/hardware-buffer-overflow-defenses.html https://lazytyped.blogspot.com/2016/12/hardware-buffer-overf... ARM v8.5 memory tagging extensions aims to try to achieve parity with it. https://www.youtube.com/watch?v=IbisEjzoxTY https://www.youtube.com/watch?v=IbisEjzoxTY Google is planning to make use of them on the native layer of Android when they eventually became available. Meanwhile Intel has decided to remove MPX from x86/x64 because no one is adopting them on Intel/AMD CPUs. EDIT: Got the ARM version wrong.
- headmelted 8y agoEven with this being true, Wave are clearly open-sourcing MIPS because of the buzz around RISC-V. In all likelihood, MIPS would have changed hands a few more times then been shelved indefinitely by an ultimate licensor that saw no further value in it. In any case it's good news - MIPS support in Linux is already fairly decent so having multiple, credible open-source vendors in the space should be good for competition and adoption.
- boznz 8y agoYou can buy MIPS processors starting at 80c. I dont see that as an irrelevance.