6 ms·
> “Had this happened two or three years ago, RISC-V would have never been born.” Had RISC-V not been born, MIPS wouldn't have made this announcement.
by jf 8y ago
> “Had this happened two or three years ago, RISC-V would have never been born.”
Had RISC-V not been born, MIPS wouldn't have made this announcement.
- SlowRobotAhead 8y agomindblown.gif :) I guess the thing that has put me off of RISCV is The emphasis on for peripherals, they’re just doesn’t seem to be a lot. Yeah, there’s a peripheral bus, And I’m sure it works great but… This is where I could see MIPS going open source to have a serious advantage. There are people out there that already have experience with how MIPS peripherals should work.
- monocasa 8y agoMIPS isn't really known for peripherals either.
- kevin_thibedeau 8y agoModern MIPS implementations usually have AMBA support.
- monocasa 8y agoAnd there's open TileLink->AMBA bridges too if that counts.
- ac29 8y agoMIPS was on its way to irrelevance, first as ARM slowly ate its remaining marketshare, then quickly when Imagination Technology went under and sold it off for a pittance to a relatively obscure "AI" company. RISC-V may have hastened its demise, but the writing was on the wall for a long time.
- chasil 8y agoI don't program in assembler professionally, but I understand that MIPS has some ugly, ugly aspects: https://www.jwhitham.org/2016/02/risc-instruction-sets-i-have-known-and.html https://www.jwhitham.org/2016/02/risc-instruction-sets-i-hav... Sun opened the SPARC T2 a decade ago, and it certainly has not become popular: https://www.oracle.com/technetwork/systems/opensparc/opensparc-t2-page-1446157.html https://www.oracle.com/technetwork/systems/opensparc/openspa... It does seem that RISC-V corrects a number of these design eccentricities. SPARC did not move the market an inch with an open release - perhaps MIPS will fail just as spectacularly.
- walterbell 8y agoThere are large numbers of consumer MIPS devices (routers) in existence, which run mature open-source software stacks. Future iterations of MIPS can be governed by a multi-stakeholder community, avoiding past mistakes and designing for future requirements, including AI/ML and other domain-specific use cases.
- snaky 8y agoAh, those mature MIPS routers https://news.ycombinator.com/item?id=18688947 https://news.ycombinator.com/item?id=18688947
- walterbell 8y agoYep :) They can be fixed with a software update.
- rasz 8y agoCan, but wont.
- bcaa7f3a8bbc 8y agoMIPS is mature, all the toolchains are here. It's simply that most vendors are too incompetent to care, as it doesn't affect their revenue in any way. > Security and Hardening by Steven Barth - OpenWrt Summit > Introducing new and ongoing security improvements to bleeding edge OpenWrt. This talk describes the new default toolchain featuring musl libc, enabled hardening including ASLR, SSP as well as OpenWrt's novel jailing (jailfs and seccomp) and package signing features (based on Curve25519). > https://www.youtube.com/watch?v=DNYvIrI5Bbs https://www.youtube.com/watch?v=DNYvIrI5Bbs On the other hand, OpenWrt implemented full system-wide ASLR recently. NX and jailfs is still a WIP.
- IntelMiner 8y agoI've heard a lot of people say RISC-V is very "MIPS Like" as well Just minus a lot of the "legacy baggage"
- msla 8y agoRISC-V's integer multiplication extension doesn't do the lo/hi trick MIPS did, and it doesn't specify a latency; that is, the integer multiplication opcode, if your chip has one, returns its value in a normal register, not split into a special lo register for the low bits and hi for the high bits, and it executes in a normal sequence with the others from a software perspective, as opposed to MIPS, where it was specified to execute sychronously with the normal instruction stream, and you'd only stall the pipeline if you tried to read lo or hi too early after the mutiplication opcode had issued, before the actual arithmetic was completed. https://stackoverflow.com/questions/27893526/mips-are-some-assembly-instructions-faster-than-others https://stackoverflow.com/questions/27893526/mips-are-some-a... > Programming Notes: > In some processors the integer multiply operation may proceed asynchronously and allow other CPU instructions to execute before it is complete. An attempt to read LO or HI before the results are written interlocks until the results are ready. Asynchronous execution does not affect the program result, but offers an opportunity for performance improvement by scheduling the multiply so that other instructions can execute in parallel. Programs that require overflow detection must check for it explicitly. > Where the size of the operands are known, software should place the shorter operand in GPR rt. This may reduce the latency of the instruction on those processors which implement data-dependent instruction latencies. (MIPS32TM Architecture For Programmers Volume II: The MIPS32TM Instruction Set, mul / mult instrutions) It's... a bit more low-level than assembly ISAs are typically designed to be these days.
- ajross 8y agoFWIW, if I had to pick the "biggest differences from MIPS" in RISC-V, it wouldn't be the fact that MUL works on GPRs. More important is the lack of a branch delay slot (i.e. it doesn't bake in a particular pipeline stage design into the ISA), and the existence of hardware paging (MIPS tried to cheat here by letting software handle page faults, and in hindsight made a poor decision).
- reirob 8y agoFrom the article: > Linley Gwennap, principal analyst at the Linley Group, told EE Times, “MIPS is certainly behind RISC-V in mindshare in the open-source community.” He noted that MIPS was “unable to make this move sooner due to its various ownership transitions.”
- DannyBee 8y agoCompletely right. Also, it's too late. The people who think "there's still time" completely misread the situation. Same with the "maturity" argument. None of these plans are a surprise to anyone. MIPS has been working on this for quite a while. Yet they have exactly zero announcement partners saying they plan on doing something with it. That's because none of them care at this point. (Also, it will take a year or two before any of this is real in a way a partner might be able to use/contribute to/care about etc) The only meaningful thing that will happen here is people will try to use it to leverage the stuff they want out of risc-v to happen.
- hardwaresofton 8y agoI personally hope this doesn't distract from the hype and progress around RISC-V. I'm very biased against companies/tech projects that go open source as a last ditch attempt to stay in competition when it's clear that an open source solution is gaining steam/mindshare -- it always seems disingenuous.
- azinman2 8y agoWould you rather it stay closed?
- hardwaresofton 8y agoI don't know -- the obvious answer is no (more code in full view is better than less), but when I think about it, you have to weigh the benefits against possible damage to RISC-V or more F/OSS aligned competitors. I have no way of knowing of course, but if MIPS simply went open source but don't actually think the same way RISC-V does, then they might lure enthusiasts that would have worked on RISC-V. That's the point I hoped to make -- if the result is fragmentation and slowed progress on RISC-V because of a muddying of the waters as to who thinks what about F/OSS then that is a bad outcome in my eyes.
- neltnerb 8y agoTo what extent can RISC-V adopt ideas from MIPS, assuming compatible licenses? Is it not really transferable because of core differences?