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Disregarding the fanboyism, we all must thank AMD for the advances and much better deals we are getting these days. 2 years ago, Intel was laughing at "glued-t

Disregarding the fanboyism, we all must thank AMD for the advances and much better deals we are getting these days. 2 years ago, Intel was laughing at "glued-together" CPUs, rolling their eyes at anything with more than 4 cores and more recently implying that CPUs with different process sizes was "cheating". Look at them now..

pozzed420 8y ago
Put down your AMD-branded crack pipe. Intel was talking about EMIB and moving parts of the uncore to old process nodes since 2014: http://semimd.com/blog/2014/09/02/intel-announces-new-interconnect-for-14nm/ http://semimd.com/blog/2014/09/02/intel-announces-new-interc... https://www.intel.com/content/www/us/en/foundry/emib.html https://www.intel.com/content/www/us/en/foundry/emib.html https://www.extremetech.com/computing/254728-intel-discusses-new-emib-packaging-technology-can-mesh-different-process-nodes-package https://www.extremetech.com/computing/254728-intel-discusses... https://www.storagereview.com/intel_unveils_its_stratix_10_mx_fpga_with_integrated_hbm2 https://www.storagereview.com/intel_unveils_its_stratix_10_m...
- z_ 8y ago
  So its taken Intel, the market leader, five or more years to release a competing product? Edit: typo
- alluro2 8y ago
  Key word being "talking".
blackstrips 8y ago
> more recently implying that CPUs with different process sizes was "cheating". Not sure where you heard that because Intel’s CPUs have different feature sizes among the layers. It’s done to cut cost. There is a downside to “glued-together” CPUs as Zen has demonstrated - their L3 cache is splitted and connected by a relatively slow connection. I hope Intel continues to make “non-split” CPUs where all cores have equal access to single huge L3 cache. As for moving components off die ... IIRC the Pentium Pro has its L2 cache on a different die but in the same package and the Pentium 2 went even further with the L2 cache on a daughterboard. This isn’t new to anyone.
- rbanffy 8y ago
  Unisys Micro-A desktop mainframe had, IIRC, 7 chips in the same package. It was quite remarkable.

pozzed420 8y ago

Put down your AMD-branded crack pipe. Intel was talking about EMIB and moving parts of the uncore to old process nodes since 2014: http://semimd.com/blog/2014/09/02/intel-announces-new-interconnect-for-14nm/ http://semimd.com/blog/2014/09/02/intel-announces-new-interc... https://www.intel.com/content/www/us/en/foundry/emib.html https://www.intel.com/content/www/us/en/foundry/emib.html https://www.extremetech.com/computing/254728-intel-discusses-new-emib-packaging-technology-can-mesh-different-process-nodes-package https://www.extremetech.com/computing/254728-intel-discusses... https://www.storagereview.com/intel_unveils_its_stratix_10_mx_fpga_with_integrated_hbm2 https://www.storagereview.com/intel_unveils_its_stratix_10_m...

z_ 8y ago
So its taken Intel, the market leader, five or more years to release a competing product? Edit: typo
alluro2 8y ago
Key word being "talking".

blackstrips 8y ago

> more recently implying that CPUs with different process sizes was "cheating". Not sure where you heard that because Intel’s CPUs have different feature sizes among the layers. It’s done to cut cost. There is a downside to “glued-together” CPUs as Zen has demonstrated - their L3 cache is splitted and connected by a relatively slow connection. I hope Intel continues to make “non-split” CPUs where all cores have equal access to single huge L3 cache. As for moving components off die ... IIRC the Pentium Pro has its L2 cache on a different die but in the same package and the Pentium 2 went even further with the L2 cache on a daughterboard. This isn’t new to anyone.

rbanffy 8y ago
Unisys Micro-A desktop mainframe had, IIRC, 7 chips in the same package. It was quite remarkable.