Alternatively 3DIC invites power efficient architectures which scale transistors over power per transistor. Such that you might have many more processor cores /

Alternatively 3DIC invites power efficient architectures which scale transistors over power per transistor. Such that you might have many more processor cores / stream processors, clocked much slower, at lower voltages. The real problem as I see it, is that producing 3D chips is uneconomical for most cases. You either need to stack dies (expensive), or produce layers of transistors, incurring more lithography / etch / mask steps (slow and expensive). So it mainly makes economical sense in area constrained scenarios.