... so what? most code's hot and should be issued from the uop cache at 6uop/cl with "80%+ hit rate" from your source you're really not making the case that "d

... so what? most code's hot and should be issued from the uop cache at 6uop/cl with "80%+ hit rate" from your source you're really not making the case that "decode" is the bottleneck, are you unaware of the mitigations that x86 designs have taken to alleviate that? or are those mitigations your proof that the ISA's deficient