This is a bit of a misrepresentation. The only flash that never had ECC was NOR. Some embedded systems had NOR, but I'd be incredibly rare to find a consumer SS

This is a bit of a misrepresentation. The only flash that never had ECC was NOR. Some embedded systems had NOR, but I'd be incredibly rare to find a consumer SSD with NOR. When designing a NAND memory product, you aim for some max allowed error rate. You choose the error correction algorithm based on that target. Error rates for NAND products are precisely what the designer intended. Because SSDs are so large and there is such a large number of them, errors can still occur (at a known rate). FTLs should take that into account. Critical data structures can add checksum redundancy which can reduce the error rate for those to an even lower value, which is usually necessary anyway since power disturbances during erase or program can cause programming errors. There are of course a number of patterns that increase error rates that FTLs have to be programmed to prevent. Encrypting is the first important step, since it makes the data unlikely to be uniform. The second is mitigating read disturb.