4 ms·
That's not the case. Only one of Skylake's decoders can translate complex x86 instructions. The other 4 are simple decoders, and can only transform a simple x86
by chroma 8y ago
That's not the case. Only one of Skylake's decoders can translate complex x86 instructions. The other 4 are simple decoders, and can only transform a simple x86 instruction into a single µop. At most, Skylake's decoder can emit 5 µops per cycle.[1]
1. https://en.wikichip.org/wiki/intel/microarchitectures/skylake_(client)#Decoding https://en.wikichip.org/wiki/intel/microarchitectures/skylak...
- jawnv6 8y ago... so what? most code's hot and should be issued from the uop cache at 6uop/cl with "80%+ hit rate" from your source you're really not making the case that "decode" is the bottleneck, are you unaware of the mitigations that x86 designs have taken to alleviate that? or are those mitigations your proof that the ISA's deficient