Yeah I dunno this doesn't seem unusual to me, for instance here is RIOS aka POWER1 from 1989 http://ps-2.kev009.com/ohlandl/RS6000/RS6000_RISC_Chipset.html http

Yeah I dunno this doesn't seem unusual to me, for instance here is RIOS aka POWER1 from 1989 http://ps-2.kev009.com/ohlandl/RS6000/RS6000_RISC_Chipset.html http://ps-2.kev009.com/ohlandl/RS6000/RS6000_RISC_Chipset.ht.... It's possible to get 4 instructions per clock (a branch, a condition-register instruction, a fixed-point instruction, and a floating-point instruction) as well as a FMA (fused-multiply add) going on this implementation. Later implementations greatly improved the ILP from there. More ugh is something like managing delay slots which MIPS and other common chips used in the 1990s consoles used https://en.wikipedia.org/wiki/Delay_slot https://en.wikipedia.org/wiki/Delay_slot. POWER is a much nicer and post-modern ISA so I think the 2000s era consoles were a lot easier to develop for.