7 ms·

Although the video is short and may not reveal everything about the chip, the chip appears anything but tricky or complex. Seems like it would be fun to optimiz

Although the video is short and may not reveal everything about the chip, the chip appears anything but tricky or complex. Seems like it would be fun to optimize for.

Izmaki 8y ago
Did you skip the part where he told that 6 instructions are being executed in parallel per cycle or is this not tricky in your opinion?
- mepian 8y ago
  That's not uncommon for DSP chips.
- a1369209993 8y ago
  Those six instructions amount to: # a += (*p++) * (*q++) mov x qi , mov y pi , mov b p*q , add , mov a a+b , [fiddle with index registers or store result] It only looks tricky because the operation is manually scheduled onto a fairly deep pipeline, so each unit is doing its phase of a different iteration of the loop in any given cycle.
- kev009 8y ago
  Yeah I dunno this doesn't seem unusual to me, for instance here is RIOS aka POWER1 from 1989 http://ps-2.kev009.com/ohlandl/RS6000/RS6000_RISC_Chipset.html http://ps-2.kev009.com/ohlandl/RS6000/RS6000_RISC_Chipset.ht.... It's possible to get 4 instructions per clock (a branch, a condition-register instruction, a fixed-point instruction, and a floating-point instruction) as well as a FMA (fused-multiply add) going on this implementation. Later implementations greatly improved the ILP from there. More ugh is something like managing delay slots which MIPS and other common chips used in the 1990s consoles used https://en.wikipedia.org/wiki/Delay_slot https://en.wikipedia.org/wiki/Delay_slot. POWER is a much nicer and post-modern ISA so I think the 2000s era consoles were a lot easier to develop for.
- RantyDave 8y ago
  It's tricky, but it's basically a dedicated coprocessor for matrix maths. So this gnarly little piece of code is probably one of the half dozen pretty-much-stock examples of what you can actually do with the thing and once you've got it going, you just leave it alone.
- nielsbot 8y ago
  Is this really under control of the programmer? Sounds like a "we need a smarter compiler" problem...
  - carlmr 8y ago
    Writing a smart compiler for such a special application would have probably cost more time. This unit was specifically used (from what I can gather) for matrix multiplications, so the average Sega programmer didn't actually touch the code it was running.
    - nielsbot 8y ago
      Thanks. Not sure why I was downvoted. What is this, stack overflow?
      - carlmr 8y ago
        I don't know either, people are judgmental I guess?
nielsbot 8y ago
So it's VLIW?
tjalfi 8y ago
[0] is a manual for the DSP assembler. It has a few example programs. [0] https://antime.kapsi.fi/sega/files/ST-240-A-042795.pdf https://antime.kapsi.fi/sega/files/ST-240-A-042795.pdf

Although the video is short and may not reveal everything about the chip, the chip appears anything but tricky or complex. Seems like it would be fun to optimize for.

Izmaki 8y ago

Did you skip the part where he told that 6 instructions are being executed in parallel per cycle or is this not tricky in your opinion?

mepian 8y ago
That's not uncommon for DSP chips.
a1369209993 8y ago
Those six instructions amount to: # a += (*p++) * (*q++) mov x qi , mov y pi , mov b p*q , add , mov a a+b , [fiddle with index registers or store result] It only looks tricky because the operation is manually scheduled onto a fairly deep pipeline, so each unit is doing its phase of a different iteration of the loop in any given cycle.
kev009 8y ago
Yeah I dunno this doesn't seem unusual to me, for instance here is RIOS aka POWER1 from 1989 http://ps-2.kev009.com/ohlandl/RS6000/RS6000_RISC_Chipset.html http://ps-2.kev009.com/ohlandl/RS6000/RS6000_RISC_Chipset.ht.... It's possible to get 4 instructions per clock (a branch, a condition-register instruction, a fixed-point instruction, and a floating-point instruction) as well as a FMA (fused-multiply add) going on this implementation. Later implementations greatly improved the ILP from there. More ugh is something like managing delay slots which MIPS and other common chips used in the 1990s consoles used https://en.wikipedia.org/wiki/Delay_slot https://en.wikipedia.org/wiki/Delay_slot. POWER is a much nicer and post-modern ISA so I think the 2000s era consoles were a lot easier to develop for.
RantyDave 8y ago
It's tricky, but it's basically a dedicated coprocessor for matrix maths. So this gnarly little piece of code is probably one of the half dozen pretty-much-stock examples of what you can actually do with the thing and once you've got it going, you just leave it alone.
nielsbot 8y ago
Is this really under control of the programmer? Sounds like a "we need a smarter compiler" problem...
- carlmr 8y ago
  Writing a smart compiler for such a special application would have probably cost more time. This unit was specifically used (from what I can gather) for matrix multiplications, so the average Sega programmer didn't actually touch the code it was running.
  - nielsbot 8y ago
    Thanks. Not sure why I was downvoted. What is this, stack overflow?
    - carlmr 8y ago
      I don't know either, people are judgmental I guess?

nielsbot 8y ago

So it's VLIW?

tjalfi 8y ago

[0] is a manual for the DSP assembler. It has a few example programs. [0] https://antime.kapsi.fi/sega/files/ST-240-A-042795.pdf https://antime.kapsi.fi/sega/files/ST-240-A-042795.pdf