It will never be able to simulate encrypted RTL - so any design using vendor IP is out (so lots of Xilinx cores, for example). It is a cycle simulator (not a de

It will never be able to simulate encrypted RTL - so any design using vendor IP is out (so lots of Xilinx cores, for example). It is a cycle simulator (not a delta time simulator), so no back annotated timing is possible. It does not support mixed language simulation (I know, it is a Verilog simulator, but you don't always get to choose what language a vendor supplies IP in). So that's just to start. Writing C++ to toggle clocks then force the simulator to re-evaluate everything is terrible (opinion). The primary tutorials I've found are Dan Gisselquest's (ZipCpu) and (iirc) he recommends running your testbench in a delta simulator as well, to make sure it's giving you what you expect. So it isn't much of a "standalone" tool. All that said, it seems like it could be useful - it wasn't in my case, but ymmv.