A bit of unrelated, but since it is important for chips development posting it here. There is an initiative [1] to make FPGA/ASIC design tooling more universal

A bit of unrelated, but since it is important for chips development posting it here. There is an initiative [1] to make FPGA/ASIC design tooling more universal and interconnected with sharing the LLVM-like low level intermediate representation (HDL), which is more powerful than Verilog or VHDL. At this point many people see FIRRTL[2][3] as a viable candidate for this position, with some enhancements. [1] https://github.com/SymbiFlow/ideas/issues/19 https://github.com/SymbiFlow/ideas/issues/19 [2] https://bar.eecs.berkeley.edu/projects/firrtl.html https://bar.eecs.berkeley.edu/projects/firrtl.html [3] https://github.com/freechipsproject/FIRRTL https://github.com/freechipsproject/FIRRTL