I'm not sure about resources but I can explain the basics. BTI happens when there is a constant voltage across the gate/source of a transistor for a long time.

I'm not sure about resources but I can explain the basics. BTI happens when there is a constant voltage across the gate/source of a transistor for a long time. An example for a digital circuit could be an inverter held in one state. Either the pmos or nmos will have a large vgs and over time this bias will shift the threshold voltage (vt). Now if this inverter delay is critical, BTI will cause the delay to change and could break timing. To fix it if the inverter is toggled after sometime it will mostly recover to the normal delay. Some people mitigate it by having very low frequency toggling for 'off' gates, but usually only if those gates are critical/matched. Alternatively people just margin the timing for the worst case. Analog circuitry has to be designed for it also, and it's an issue in differential pairs for example.