3 ms·
Someone at UC Berkeley is already adding hardware-assisted GC to a RISC-V core: https://people.eecs.berkeley.edu/~maas/papers/maas-asbd16-hwgc.pdf https://peopl
by mepian 8y ago
Someone at UC Berkeley is already adding hardware-assisted GC to a RISC-V core: https://people.eecs.berkeley.edu/~maas/papers/maas-asbd16-hwgc.pdf https://people.eecs.berkeley.edu/~maas/papers/maas-asbd16-hw...
- FullyFunctional 8y agoI'm on the RISC-V J committee (headed by Martin Mass), but what I'm proposing here is unlikely (?) to appeal to the mainstream RISC-V SoC developers, at least not without a strong PoC.