4 ms·

I work in chip design, and we certainly don't design for planned failure, but we do design for 20 year reliability. This means we over-design to ensure reliabil

I work in chip design, and we certainly don't design for planned failure, but we do design for 20 year reliability. This means we over-design to ensure reliability up to 20 years. If a market does not need such longevity then it would be reasonable to design for less time, to ensure you are not over designing. Chip deign is all about trade offs - power, area, performance, reliability, flexibility, integration cost, high/low temperature operation, yield, etc - and designing for 20 years certainly impacts this trade off.

agumonkey 8y ago
What's the upper limit of longevity testing, say for space use, 100 years ?
- tails4e 8y ago
  Good question, it depends on a few factors - e.g. BTI is aging that alters the transistor performance over time when a transistor has a fixed bias, so if you've loads of margin for this it should not impact you, or you can mitigate by periodically altering the bias to recover. TDDB is an issue at higher than normal voltages, so of the environment is controlled this can be avoided. For high reliability situations older process nodes are usually used which are less susceptible to these failures, and the environment is well controlled. Space has other issues like much higher probability of random bit flips, so design for space is challenging. Note our 20 year lifetime also assumes worst case conditions, so I'd wager many of our chips would last much longer in practice.
  - new299 8y ago
    What does changing the bias to recover look like in practice? Any resources on this?
    - tails4e 8y ago
      I'm not sure about resources but I can explain the basics. BTI happens when there is a constant voltage across the gate/source of a transistor for a long time. An example for a digital circuit could be an inverter held in one state. Either the pmos or nmos will have a large vgs and over time this bias will shift the threshold voltage (vt). Now if this inverter delay is critical, BTI will cause the delay to change and could break timing. To fix it if the inverter is toggled after sometime it will mostly recover to the normal delay. Some people mitigate it by having very low frequency toggling for 'off' gates, but usually only if those gates are critical/matched. Alternatively people just margin the timing for the worst case. Analog circuitry has to be designed for it also, and it's an issue in differential pairs for example.

agumonkey 8y ago

What's the upper limit of longevity testing, say for space use, 100 years ?

tails4e 8y ago
Good question, it depends on a few factors - e.g. BTI is aging that alters the transistor performance over time when a transistor has a fixed bias, so if you've loads of margin for this it should not impact you, or you can mitigate by periodically altering the bias to recover. TDDB is an issue at higher than normal voltages, so of the environment is controlled this can be avoided. For high reliability situations older process nodes are usually used which are less susceptible to these failures, and the environment is well controlled. Space has other issues like much higher probability of random bit flips, so design for space is challenging. Note our 20 year lifetime also assumes worst case conditions, so I'd wager many of our chips would last much longer in practice.
- new299 8y ago
  What does changing the bias to recover look like in practice? Any resources on this?
  - tails4e 8y ago
    I'm not sure about resources but I can explain the basics. BTI happens when there is a constant voltage across the gate/source of a transistor for a long time. An example for a digital circuit could be an inverter held in one state. Either the pmos or nmos will have a large vgs and over time this bias will shift the threshold voltage (vt). Now if this inverter delay is critical, BTI will cause the delay to change and could break timing. To fix it if the inverter is toggled after sometime it will mostly recover to the normal delay. Some people mitigate it by having very low frequency toggling for 'off' gates, but usually only if those gates are critical/matched. Alternatively people just margin the timing for the worst case. Analog circuitry has to be designed for it also, and it's an issue in differential pairs for example.