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>Changing the addressing schema completely solved the issue. Can you elaborate at all? Do you mean you changing the FPGA to not write to exactly the same spots
by SlowRobotAhead 8y ago
>Changing the addressing schema completely solved the issue.
Can you elaborate at all? Do you mean you changing the FPGA to not write to exactly the same spots over and over? And just set up something up similar to wear leveling?
- leghifla 8y agoIt was very simple, I kept all the "logical" addresses the same, but swapped some low address bits with high address bits at the memory controller interface. With this, the slowly moving indexes became big jumps. This avoids reading the same row over and over again (mixed with other requests).
- avianes 8y ago> This avoids reading the same row over and over again Didn't you notice a huge drop in performance producing row-buffer conflicts over and over ?
- leghifla 8y agoGood question. Jumping around the memory is clearly not good for throughput. Before the change, the mixing of requests between processes was already detrimental for performance anyway. All I can say is that we needed a fixed bandwidth and it was enough, before or after the change.