An article I read awhile ago addressed an interesting correlation between transistor process size, the physical size of the dram module and the expected failure

An article I read awhile ago addressed an interesting correlation between transistor process size, the physical size of the dram module and the expected failure rates. "As transistor sizes have shrunk, they have required less and less electrical charge to represent a logical bit. So the likelihood that one bit will "flip" from 0 to 1 (or 1 to 0) when struck by an energetic particle has been increasing. This has been partially offset by the fact that as the transistors have gotten smaller they have become smaller targets so the rate at which they are struck has decreased. More significantly, the current generation of 16-nanometer circuits have a 3D architecture that replaced the previous 2D architecture and has proven to be significantly less susceptible to SEUs. Although this improvement has been offset by the increase in the number of transistors in each chip, the failure rate at the chip level has also dropped slightly. However, the increase in the total number of transistors being used in new electronic systems has meant that the SEU failure rate at the device level has continued to rise." [1] https://phys.org/news/2017-02-particles-outer-space-wreaking-low-grade.html https://phys.org/news/2017-02-particles-outer-space-wreaking...