3 ms·
> meaning 256-bit AVX operations no longer need to be cracked into two 128-bit micro-ops per instruction The instruction set stayed the same. And in the curren
by Const-me 8y ago
> meaning 256-bit AVX operations no longer need to be cracked into two 128-bit micro-ops per instruction
The instruction set stayed the same. And in the current instruction set, a lot of these AVX instruction still operate on 128 bit lanes. Instructions like vpshufd, vshufps, vpblendw only shuffle/blend/permute within 128-bit lanes, so do AVX512 equivalents.
- Tuna-Fish 8y agoYes, but that was not what the article was referring to. Zen1 CPUs only have 128-bit FPU lanes, and execute wider instructions by splitting them into two in the frontend.