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Anyone know why we aren't seeing Intel/AMD go the 'ultra-wide' route that we've seen in ARM processors? (Apple's in particular) e.g. we've seen Apple's A12 pro

by mbell 8y ago

Anyone know why we aren't seeing Intel/AMD go the 'ultra-wide' route that we've seen in ARM processors? (Apple's in particular) e.g. we've seen Apple's A12 processor expand ALU's from 4->6 and what seems like a strong focus on cache latency and these changes seem to be rather beneficial in real code. Why aren't we seeing the same from Intel / AMD? As someone whom isn't particularly well informed on the topic my guess is that AMD/Intel are scared of selling a wider-core but lower clocked CPU given how much marketing is attached to clock speed, but I imagine there are architectural issues as well.

hmottestad 8y ago
Is Apple ahead of x86/64 on width? The A10X article on anandtech seemed to imply that every other ARM architecture was far behind on width while Apple was mostly on par (or slightly behind) x86/64.
- mbell 8y ago
  Apple doesn't release the details but Anandtech estimates A12 has 13 execution ports (https://www.anandtech.com/show/13392/the-iphone-xs-xs-max-review-unveiling-the-silicon-secrets/3 https://www.anandtech.com/show/13392/the-iphone-xs-xs-max-re...). I'm guessing the numbers for 6 ALU ports are more accurate than the overall since it's hard to blackbox determine the port sharing structure. Recent Intel / Zen have 4 ALU ports AFAIK.
- coder543 8y ago
  A10X or A12X? But there are a number of benchmarks showing the A12X outperforming most of Apple's laptop lineup and many competitors. The A12X doesn't have the liberty of a desktop form factor, so it is definitely a mobile part, but it seems reasonable that Apple could make another chip that scales the performance up even further if they wanted to, without really altering the underlying architecture.
BeeOnRope 8y ago
Well AMD has gone wider - to 5 or 6 wide depending on how you count it in Ryzen. Intel hasn't really been able to make any changes to make any major uarch changes in years, since they've been stuck on Skylake (and all the various Skylake++ variants that followed which were Skylake in name only). In Skylake, most of the effort seemed focused on bringing AVX-512 to bear, and outside of that the basic design is largely the same as Haswell. Here's hoping that Apple's chips portend an increase in width in mainstream x86 chips as well.
- shaklee3 8y ago
  Skylake also got rid of the ring core architecture, and went to the grid. That was a pretty drastic change, and very different from their previous generations.
  - BeeOnRope 8y ago
    Yes, true - that showed up in the SKX uncore. I wonder if it is being used in CNL client parts as well?
blattimwind 8y ago
Intel cores have had eight EU ports since Haswell. Zen has a split pipeline, so it's not comparable. Zen has ten units, some µops use multiple EUs (e.g. AGU and ALU).
deleted 8y ago
[deleted]
phkahler 8y ago
Instruction set and the number of registers visible to the programmer influence the practical limits to issue width. AMD64 (x86_64) only has 16 general purpose registers, so there are limits to how many instructions could possibly execute at one time. If I recall correctly the ARM ISA has 32 registers, so there is potential for a lot more data sitting there ready to do something on any given cycle. There are limits imposed by software as well - lots of real world program code simply doesn't have opportunities to do many things in parallel. Having said all that, any extra execution units can be used more effectively with multi-threading. It sounds neat to have twice as many threads as cores, but on my workloads that's only about a 20 percent performance increase. Going wider would probably help the second thread quite a bit, but what would be sacrificed is deep in the details of a given design. I suspect they increase width so long as it doesn't impact single thread performance.
- ahartmetz 8y ago
  Only somewhat true. There is register renaming which increases the size of the virtual register set. rax assigned to in line 1 can be a different virtual register from rax assigned to in line 5. AMD and Intel should both be very good at exploiting it to the limits, they had to in their superscalar 32 bit x86 designs :)
- monocasa 8y ago
  I've heard from a CPU designer that the CISC nature of x86 lets it punch above it's weight in terms of what you're talking about. There's a lot of instructions that don't reference any architectural registers, but get allocated physical registers (and would have architectural registers allocated when compiled to something RISC). He claimed it was about equivalent to a 32 register RISC for that reason.
  - phkahler 8y ago
    x86 has plenty of instructions that use data from memory as one of the operands. I'm sure that offsets the limited number of registers somewhat. In the end it's all deep in the details. What I'd really like to see is a RISC-V implementation done by a full team at Intel, AMD, or IBM. Even an ARM implementation by those teams would make a great comparison, but that seems even less likely ;-)

by mbell 8y ago

hmottestad 8y ago

Is Apple ahead of x86/64 on width? The A10X article on anandtech seemed to imply that every other ARM architecture was far behind on width while Apple was mostly on par (or slightly behind) x86/64.

mbell 8y ago
Apple doesn't release the details but Anandtech estimates A12 has 13 execution ports (https://www.anandtech.com/show/13392/the-iphone-xs-xs-max-review-unveiling-the-silicon-secrets/3 https://www.anandtech.com/show/13392/the-iphone-xs-xs-max-re...). I'm guessing the numbers for 6 ALU ports are more accurate than the overall since it's hard to blackbox determine the port sharing structure. Recent Intel / Zen have 4 ALU ports AFAIK.
coder543 8y ago
A10X or A12X? But there are a number of benchmarks showing the A12X outperforming most of Apple's laptop lineup and many competitors. The A12X doesn't have the liberty of a desktop form factor, so it is definitely a mobile part, but it seems reasonable that Apple could make another chip that scales the performance up even further if they wanted to, without really altering the underlying architecture.

BeeOnRope 8y ago

Well AMD has gone wider - to 5 or 6 wide depending on how you count it in Ryzen. Intel hasn't really been able to make any changes to make any major uarch changes in years, since they've been stuck on Skylake (and all the various Skylake++ variants that followed which were Skylake in name only). In Skylake, most of the effort seemed focused on bringing AVX-512 to bear, and outside of that the basic design is largely the same as Haswell. Here's hoping that Apple's chips portend an increase in width in mainstream x86 chips as well.

shaklee3 8y ago
Skylake also got rid of the ring core architecture, and went to the grid. That was a pretty drastic change, and very different from their previous generations.
- BeeOnRope 8y ago
  Yes, true - that showed up in the SKX uncore. I wonder if it is being used in CNL client parts as well?

blattimwind 8y ago

Intel cores have had eight EU ports since Haswell. Zen has a split pipeline, so it's not comparable. Zen has ten units, some µops use multiple EUs (e.g. AGU and ALU).

deleted 8y ago

[deleted]

phkahler 8y ago

Instruction set and the number of registers visible to the programmer influence the practical limits to issue width. AMD64 (x86_64) only has 16 general purpose registers, so there are limits to how many instructions could possibly execute at one time. If I recall correctly the ARM ISA has 32 registers, so there is potential for a lot more data sitting there ready to do something on any given cycle. There are limits imposed by software as well - lots of real world program code simply doesn't have opportunities to do many things in parallel. Having said all that, any extra execution units can be used more effectively with multi-threading. It sounds neat to have twice as many threads as cores, but on my workloads that's only about a 20 percent performance increase. Going wider would probably help the second thread quite a bit, but what would be sacrificed is deep in the details of a given design. I suspect they increase width so long as it doesn't impact single thread performance.

ahartmetz 8y ago
Only somewhat true. There is register renaming which increases the size of the virtual register set. rax assigned to in line 1 can be a different virtual register from rax assigned to in line 5. AMD and Intel should both be very good at exploiting it to the limits, they had to in their superscalar 32 bit x86 designs :)
monocasa 8y ago
I've heard from a CPU designer that the CISC nature of x86 lets it punch above it's weight in terms of what you're talking about. There's a lot of instructions that don't reference any architectural registers, but get allocated physical registers (and would have architectural registers allocated when compiled to something RISC). He claimed it was about equivalent to a 32 register RISC for that reason.
- phkahler 8y ago
  x86 has plenty of instructions that use data from memory as one of the operands. I'm sure that offsets the limited number of registers somewhat. In the end it's all deep in the details. What I'd really like to see is a RISC-V implementation done by a full team at Intel, AMD, or IBM. Even an ARM implementation by those teams would make a great comparison, but that seems even less likely ;-)