Yes, this is a reasonable explanation of the ARM and Intel memory models, but I'm not following how this relates to miss buffers specifically. The load buffers

Yes, this is a reasonable explanation of the ARM and Intel memory models, but I'm not following how this relates to miss buffers specifically. The load buffers which maintain the source/program ordering on a per-instruction basis as you describe above are called ... load buffers. These are different than the "miss buffers" which track outstanding misses. Intel chips have 70+ load buffers, so no there is no shortage there. Yes, x86 chips have to jump through a bunch of to keep ordering, which means their load buffers probably need to more sophisticated (Intel sometimes refers to a MOB - a "memory order buffer" which tracks this stuff, but as far as I can tell this is not a separate buffer but just another name for the load and store buffers and associated machinery, with a focus on the memory ordering aspect). The way it works in Intel is that everything will speculatively execute out of order, loads passing loads and all the things the memory model doesn't officially allow, but the load buffer will track the original order. As long as there is not indication of an actual problem with the ordering (i.e., a store on another core which causes a snoop that hits the load buffer on this core), the out-of-order nature of the execution isn't visible, so everything can retire fine. If something happens that violates the order, a "MOB machine clear" happens (with a cost similar to a branch misprediction) occurs and the chip starts over. None of this directly implicates the miss buffers though. For one thing, they are not 1:1 with instructions and they are not instruction ordered, since multiple misses will coalesce to the same buffer. That said, I can certainly see the stronger x86 memory model playing a role here, but it isn't clear to me how.