Load and store queues are different than the "miss buffers" we are talking about here. Every load and store will need one of these entries from allocation until

Load and store queues are different than the "miss buffers" we are talking about here. Every load and store will need one of these entries from allocation until retirement, so there are usually a lot of them, something like 20% to 40% the size of the ROB (re-order buffer) each, since many code sequences have many loads and stores. The miss buffers are different in that they only get involved when there is an L1 miss. They are only used from the moment the miss is detected until the miss completes. Also, load and store buffers are used 1:1 with load and store instructions (including instructions that have a load, store or both combined with an ALU operation, such as load-op or RMW on x86). Miss buffers are 1:1 with outstanding misses on the granularity of cache lines. So if you load 8 consecutive 4-byte values, which all fall in the same cache line, which misses in L1, you'll have 8 load buffer entries used, but only 1 fill buffer used since the buffer coalesces all misses to the same line.