> Maybe Intel knows something we don't. Or maybe Intel's chips miss less often due to more sophisticated branch prediction and prefetching? The Pentium 4s were

> Maybe Intel knows something we don't. Or maybe Intel's chips miss less often due to more sophisticated branch prediction and prefetching? The Pentium 4s were victims of excruciatingly painful pipeline flushes and stalls. It'd make sense Intel would have invested heavily in understanding and mitigating these kinds of caching behaviors and a lot of that surely was lifted into the Nehalem/Core microarchitecture designs that most of the modern Intel chips are designed around.